# Active SVF file /net/plato.ee.Virginia.EDU/users/amk5vx/synopsys/msp430/formality/pre_layout/source/openMSP430.svf
#-----------------------------------------------------------------------------
# This file is automatically generated by Design Compiler
# Filename  : /net/plato.ee.Virginia.EDU/users/amk5vx/synopsys/msp430/dc/results/openMSP430.svf
# Timestamp : Sat Apr 28 21:47:58 2012
# DC Version: F-2011.09-SP2 (built Nov 24, 2011)
#-----------------------------------------------------------------------------

guide


guide_environment \
  { { dc_product_version F-2011.09-SP2 } \
    { dc_product_build_date { Nov 24, 2011 } } \
    { bus_dimension_separator_style ][ } \
    { bus_extraction_style %s\[%d:%d\] } \
    { bus_naming_style %s[%d] } \
    { bus_range_separator_style : } \
    { hdlin_allow_4state_parameters TRUE } \
    { hdlin_generate_naming_style %s_%d } \
    { hdlin_generate_separator_style _ } \
    { hdlin_infer_enumerated_types FALSE } \
    { hdlin_optimize_enum_types FALSE } \
    { hdlin_sv_packages enable } \
    { hdlin_vrlg_std 2005 } \
    { hdlin_while_loop_iterations 1024 } \
    { template_naming_style %s_%p } \
    { template_parameter_style %s%d } \
    { template_separator_style _ } \
    { simplified_verification_mode FALSE } \
    { link_library { * saed90nm_typ_ht.db dw_foundation.sldb } } \
    { target_library saed90nm_typ_ht.db } \
    { search_path { . /app/synopsys/CoreSynthesisTools/F-2011.12/libraries/syn /app/synopsys/CoreSynthesisTools/F-2011.12/minpower/syn /app/synopsys/CoreSynthesisTools/F-2011.12/dw/syn_ver /app/synopsys/CoreSynthesisTools/F-2011.12/dw/sim_ver ./models } } \
    { synopsys_root /app/synopsys/CoreSynthesisTools/F-2011.12 } \
    { cwd /net/plato.ee.Virginia.EDU/users/amk5vx/synopsys/msp430/dc } \
    { define_design_lib { -path ./WORK WORK } } \
    { analyze { -format verilog -library WORK \{ ./verilog/openMSP430_defines.v ./verilog/openMSP430.v ./verilog/omsp_frontend.v ./verilog/omsp_execution_unit.v ./verilog/omsp_register_file.v ./verilog/omsp_alu.v ./verilog/omsp_sfr.v ./verilog/omsp_clock_module.v ./verilog/omsp_mem_backbone.v ./verilog/omsp_watchdog.v ./verilog/omsp_dbg.v ./verilog/omsp_dbg_uart.v ./verilog/omsp_dbg_hwbrk.v ./verilog/omsp_multiplier.v ./verilog/omsp_divider_16b.v ./verilog/omsp_sync_reset.v ./verilog/omsp_sync_cell.v ./verilog/omsp_scan_mux.v ./verilog/omsp_and_gate.v ./verilog/omsp_wakeup_cell.v ./verilog/omsp_clock_gate.v ./verilog/omsp_clock_mux.v \} } } \
    { template_naming_style %s_%p } } 

guide_instance_map \
  -design { openMSP430 } \
  -instance { clock_module_0 } \
  -linked { omsp_clock_module } 

guide_mark \
  -type { svfMarkTypeBegin } \
  -phase { svfMarkPhasePresto } 

guide_info \
  -version { ./verilog/omsp_clock_module.v 7.142 } 

guide_mark \
  -type { svfMarkTypeEnd } \
  -phase { svfMarkPhasePresto } 

guide_instance_map \
  -design { openMSP430 } \
  -instance { frontend_0 } \
  -linked { omsp_frontend } 

guide_mark \
  -type { svfMarkTypeBegin } \
  -phase { svfMarkPhasePresto } 

guide_info \
  -version { ./verilog/omsp_frontend.v 7.142 } 

guide_info \
  -file \
  { { ./verilog/omsp_frontend.v 07275 } } 

guide_mark \
  -type { svfMarkTypeEnd } \
  -phase { svfMarkPhasePresto } 

guide_instance_map \
  -design { openMSP430 } \
  -instance { execution_unit_0 } \
  -linked { omsp_execution_unit } 

guide_mark \
  -type { svfMarkTypeBegin } \
  -phase { svfMarkPhasePresto } 

guide_info \
  -version { ./verilog/omsp_execution_unit.v 7.142 } 

guide_mark \
  -type { svfMarkTypeEnd } \
  -phase { svfMarkPhasePresto } 

guide_instance_map \
  -design { openMSP430 } \
  -instance { mem_backbone_0 } \
  -linked { omsp_mem_backbone } 

guide_mark \
  -type { svfMarkTypeBegin } \
  -phase { svfMarkPhasePresto } 

guide_info \
  -version { ./verilog/omsp_mem_backbone.v 7.142 } 

guide_replace \
  -origin { Presto_add0 } \
  -type { svfReplacePrestoRedundantOpRemoval } \
  -design { omsp_mem_backbone } \
  -input { 11 sub_167_lop } \
  -output { 11 sub_167_out } \
  -pre_resource { { 11 } sub_167 = SUB { { sub_167_lop ANY 11 } { U`b00000000000 } } } \
  -pre_assign { sub_167_out = { sub_167 ANY 11 } } \
  -post_assign { sub_167_out = { sub_167_lop ANY 11 } } 

guide_replace \
  -origin { Presto_add0 } \
  -type { svfReplacePrestoRedundantOpRemoval } \
  -design { omsp_mem_backbone } \
  -input { 11 sub_159_lop } \
  -output { 11 sub_159_out } \
  -pre_resource { { 11 } sub_159 = SUB { { sub_159_lop ANY 11 } { U`b00000000000 } } } \
  -pre_assign { sub_159_out = { sub_159 ANY 11 } } \
  -post_assign { sub_159_out = { sub_159_lop ANY 11 } } 

guide_replace \
  -origin { Presto_add0 } \
  -type { svfReplacePrestoRedundantOpRemoval } \
  -design { omsp_mem_backbone } \
  -input { 11 sub_163_lop } \
  -output { 11 sub_163_out } \
  -pre_resource { { 11 } sub_163 = SUB { { sub_163_lop ANY 11 } { U`b00000000000 } } } \
  -pre_assign { sub_163_out = { sub_163 ANY 11 } } \
  -post_assign { sub_163_out = { sub_163_lop ANY 11 } } 

guide_mark \
  -type { svfMarkTypeEnd } \
  -phase { svfMarkPhasePresto } 

guide_instance_map \
  -design { openMSP430 } \
  -instance { sfr_0 } \
  -linked { omsp_sfr } 

guide_mark \
  -type { svfMarkTypeBegin } \
  -phase { svfMarkPhasePresto } 

guide_info \
  -version { ./verilog/omsp_sfr.v 7.142 } 

guide_mark \
  -type { svfMarkTypeEnd } \
  -phase { svfMarkPhasePresto } 

guide_instance_map \
  -design { openMSP430 } \
  -instance { watchdog_0 } \
  -linked { omsp_watchdog } 

guide_mark \
  -type { svfMarkTypeBegin } \
  -phase { svfMarkPhasePresto } 

guide_info \
  -version { ./verilog/omsp_watchdog.v 7.142 } 

guide_mark \
  -type { svfMarkTypeEnd } \
  -phase { svfMarkPhasePresto } 

guide_instance_map \
  -design { openMSP430 } \
  -instance { multiplier_0 } \
  -linked { omsp_multiplier } 

guide_mark \
  -type { svfMarkTypeBegin } \
  -phase { svfMarkPhasePresto } 

guide_info \
  -version { ./verilog/omsp_multiplier.v 7.142 } 

guide_mark \
  -type { svfMarkTypeEnd } \
  -phase { svfMarkPhasePresto } 

guide_instance_map \
  -design { openMSP430 } \
  -instance { div0 } \
  -linked { omsp_divider_16b } 

guide_mark \
  -type { svfMarkTypeBegin } \
  -phase { svfMarkPhasePresto } 

guide_info \
  -version { ./verilog/omsp_divider_16b.v 7.142 } 

guide_mark \
  -type { svfMarkTypeEnd } \
  -phase { svfMarkPhasePresto } 

guide_instance_map \
  -design { openMSP430 } \
  -instance { dbg_0 } \
  -linked { omsp_dbg } 

guide_mark \
  -type { svfMarkTypeBegin } \
  -phase { svfMarkPhasePresto } 

guide_info \
  -version { ./verilog/omsp_dbg.v 7.142 } 

guide_mark \
  -type { svfMarkTypeEnd } \
  -phase { svfMarkPhasePresto } 

guide_instance_map \
  -design { omsp_clock_module } \
  -instance { and_cpuoff_mclk_en } \
  -linked { omsp_and_gate } 

guide_instance_map \
  -design { omsp_clock_module } \
  -instance { sync_cell_dco_disable } \
  -linked { omsp_sync_cell } 

guide_instance_map \
  -design { omsp_clock_module } \
  -instance { scan_mux_dco_wkup } \
  -linked { omsp_scan_mux } 

guide_instance_map \
  -design { omsp_clock_module } \
  -instance { clock_mux_mclk } \
  -linked { omsp_clock_mux } 

guide_instance_map \
  -design { omsp_clock_module } \
  -instance { clock_gate_mclk } \
  -linked { omsp_clock_gate } 

guide_instance_map \
  -design { omsp_clock_module } \
  -instance { sync_reset_por } \
  -linked { omsp_sync_reset } 

guide_instance_map \
  -design { omsp_execution_unit } \
  -instance { register_file_0 } \
  -linked { omsp_register_file } 

guide_mark \
  -type { svfMarkTypeBegin } \
  -phase { svfMarkPhasePresto } 

guide_info \
  -version { ./verilog/omsp_register_file.v 7.142 } 

guide_mark \
  -type { svfMarkTypeEnd } \
  -phase { svfMarkPhasePresto } 

guide_instance_map \
  -design { omsp_execution_unit } \
  -instance { alu_0 } \
  -linked { omsp_alu } 

guide_mark \
  -type { svfMarkTypeBegin } \
  -phase { svfMarkPhasePresto } 

guide_info \
  -version { ./verilog/omsp_alu.v 7.142 } 

guide_info \
  -file \
  { { ./verilog/omsp_alu.v 29325 } } 

guide_replace \
  -origin { Presto_aco } \
  -type { svfReplacePrestoConditionalAccumulation } \
  -design { omsp_alu } \
  -input { 1 src_1 } \
  -input { 1 src_2 } \
  -input { 5 src_3 } \
  -output { 5 aco_out } \
  -pre_resource { { 5 } add_102_C185 = ADD { { src_3 ZERO 5 } { U`b00110 } } } \
  -pre_resource { { 5 }  C310 = SELECT { { src_1 } { src_2 } { src_3 ZERO 5 } { add_102_C185 ZERO 5 } } } \
  -pre_assign { aco_out = {  C310 ZERO 5 } } \
  -post_resource { { 3 } concat_aco = CONCAT { { src_2 ZERO 1 } { src_2 ZERO 1 } { U`b0 } } } \
  -post_resource { { 5 } add_102_C185_aco = ADD { { src_3 ZERO 5 } { concat_aco ZERO 5 } } } \
  -post_assign { aco_out = { add_102_C185_aco ZERO 5 } } 

guide_replace \
  -origin { Presto_aco } \
  -type { svfReplacePrestoConditionalAccumulation } \
  -design { omsp_alu } \
  -input { 1 src_1 } \
  -input { 1 src_2 } \
  -input { 5 src_3 } \
  -output { 5 aco_out } \
  -pre_resource { { 5 } add_102_C186 = ADD { { src_3 ZERO 5 } { U`b00110 } } } \
  -pre_resource { { 5 }  C311 = SELECT { { src_1 } { src_2 } { src_3 ZERO 5 } { add_102_C186 ZERO 5 } } } \
  -pre_assign { aco_out = {  C311 ZERO 5 } } \
  -post_resource { { 3 } concat_aco = CONCAT { { src_2 ZERO 1 } { src_2 ZERO 1 } { U`b0 } } } \
  -post_resource { { 5 } add_102_C186_aco = ADD { { src_3 ZERO 5 } { concat_aco ZERO 5 } } } \
  -post_assign { aco_out = { add_102_C186_aco ZERO 5 } } 

guide_replace \
  -origin { Presto_aco } \
  -type { svfReplacePrestoConditionalAccumulation } \
  -design { omsp_alu } \
  -input { 1 src_1 } \
  -input { 1 src_2 } \
  -input { 5 src_3 } \
  -output { 5 aco_out } \
  -pre_resource { { 5 } add_102_C187 = ADD { { src_3 ZERO 5 } { U`b00110 } } } \
  -pre_resource { { 5 }  C312 = SELECT { { src_1 } { src_2 } { src_3 ZERO 5 } { add_102_C187 ZERO 5 } } } \
  -pre_assign { aco_out = {  C312 ZERO 5 } } \
  -post_resource { { 3 } concat_aco = CONCAT { { src_2 ZERO 1 } { src_2 ZERO 1 } { U`b0 } } } \
  -post_resource { { 5 } add_102_C187_aco = ADD { { src_3 ZERO 5 } { concat_aco ZERO 5 } } } \
  -post_assign { aco_out = { add_102_C187_aco ZERO 5 } } 

guide_replace \
  -origin { Presto_aco } \
  -type { svfReplacePrestoConditionalAccumulation } \
  -design { omsp_alu } \
  -input { 1 src_1 } \
  -input { 1 src_2 } \
  -input { 5 src_3 } \
  -output { 5 aco_out } \
  -pre_resource { { 5 } add_102_C188 = ADD { { src_3 ZERO 5 } { U`b00110 } } } \
  -pre_resource { { 5 }  C313 = SELECT { { src_1 } { src_2 } { src_3 ZERO 5 } { add_102_C188 ZERO 5 } } } \
  -pre_assign { aco_out = {  C313 ZERO 5 } } \
  -post_resource { { 3 } concat_aco = CONCAT { { src_2 ZERO 1 } { src_2 ZERO 1 } { U`b0 } } } \
  -post_resource { { 5 } add_102_C188_aco = ADD { { src_3 ZERO 5 } { concat_aco ZERO 5 } } } \
  -post_assign { aco_out = { add_102_C188_aco ZERO 5 } } 

guide_mark \
  -type { svfMarkTypeEnd } \
  -phase { svfMarkPhasePresto } 

guide_instance_map \
  -design { omsp_sfr } \
  -instance { wakeup_cell_nmi } \
  -linked { omsp_wakeup_cell } 

guide_instance_map \
  -design { omsp_dbg } \
  -instance { dbg_uart_0 } \
  -linked { omsp_dbg_uart } 

guide_mark \
  -type { svfMarkTypeBegin } \
  -phase { svfMarkPhasePresto } 

guide_info \
  -version { ./verilog/omsp_dbg_uart.v 7.142 } 

guide_mark \
  -type { svfMarkTypeEnd } \
  -phase { svfMarkPhasePresto } 

guide_environment \
  { { elaborate { -library WORK openMSP430 } } \
    { current_design openMSP430 } } 

guide_uniquify \
  -design { openMSP430 } \
  { { clock_module_0/sync_cell_dco_disable omsp_sync_cell_0 } \
    { clock_module_0/sync_cell_dco_wkup omsp_sync_cell_0 } \
    { clock_module_0/sync_cell_lfxt_disable omsp_sync_cell_0 } \
    { clock_module_0/sync_cell_lfxt_wkup omsp_sync_cell_0 } \
    { clock_module_0/sync_cell_cpu_aux_en omsp_sync_cell_0 } \
    { clock_module_0/sync_cell_cpu_sm_en omsp_sync_cell_0 } \
    { clock_module_0/sync_cell_mclk_wkup omsp_sync_cell_0 } \
    { clock_module_0/sync_cell_puc_lfxt omsp_sync_cell_0 } \
    { clock_module_0/sync_cell_oscoff omsp_sync_cell_0 } \
    { clock_module_0/sync_cell_puc_sm omsp_sync_cell_0 } \
    { clock_module_0/sync_cell_scg1 omsp_sync_cell_0 } \
    { clock_module_0/sync_cell_puc omsp_sync_cell_0 } \
    { sfr_0/sync_cell_nmi omsp_sync_cell_0 } \
    { watchdog_0/sync_cell_wdtcnt_clr omsp_sync_cell_0 } \
    { watchdog_0/sync_cell_wdtcnt_incr omsp_sync_cell_0 } \
    { watchdog_0/sync_cell_wdt_evt omsp_sync_cell_0 } \
    { dbg_0/dbg_uart_0/sync_cell_uart_rxd omsp_sync_cell_0 } \
    { clock_module_0/clock_gate_mclk omsp_clock_gate_0 } \
    { clock_module_0/clock_gate_aclk omsp_clock_gate_0 } \
    { clock_module_0/clock_gate_smclk omsp_clock_gate_0 } \
    { clock_module_0/clock_gate_dbg_clk omsp_clock_gate_0 } \
    { frontend_0/clock_gate_irq_num omsp_clock_gate_0 } \
    { frontend_0/clock_gate_pc omsp_clock_gate_0 } \
    { frontend_0/clock_gate_inst_sext omsp_clock_gate_0 } \
    { frontend_0/clock_gate_inst_dext omsp_clock_gate_0 } \
    { frontend_0/clock_gate_decode omsp_clock_gate_0 } \
    { execution_unit_0/clock_gate_mdb_out_nxt omsp_clock_gate_0 } \
    { execution_unit_0/clock_gate_mdb_in_buf omsp_clock_gate_0 } \
    { mem_backbone_0/clock_gate_bckup omsp_clock_gate_0 } \
    { watchdog_0/clock_gate_wdtctl omsp_clock_gate_0 } \
    { watchdog_0/clock_gate_wdtcnt omsp_clock_gate_0 } \
    { multiplier_0/clock_gate_op1 omsp_clock_gate_0 } \
    { multiplier_0/clock_gate_op2 omsp_clock_gate_0 } \
    { multiplier_0/clock_gate_reslo omsp_clock_gate_0 } \
    { multiplier_0/clock_gate_reshi omsp_clock_gate_0 } \
    { execution_unit_0/register_file_0/clock_gate_r1 omsp_clock_gate_0 } \
    { execution_unit_0/register_file_0/clock_gate_r2 omsp_clock_gate_0 } \
    { execution_unit_0/register_file_0/clock_gate_r3 omsp_clock_gate_0 } \
    { execution_unit_0/register_file_0/clock_gate_r4 omsp_clock_gate_0 } \
    { execution_unit_0/register_file_0/clock_gate_r5 omsp_clock_gate_0 } \
    { execution_unit_0/register_file_0/clock_gate_r6 omsp_clock_gate_0 } \
    { execution_unit_0/register_file_0/clock_gate_r7 omsp_clock_gate_0 } \
    { execution_unit_0/register_file_0/clock_gate_r8 omsp_clock_gate_0 } \
    { execution_unit_0/register_file_0/clock_gate_r9 omsp_clock_gate_0 } \
    { execution_unit_0/register_file_0/clock_gate_r10 omsp_clock_gate_0 } \
    { execution_unit_0/register_file_0/clock_gate_r11 omsp_clock_gate_0 } \
    { execution_unit_0/register_file_0/clock_gate_r12 omsp_clock_gate_0 } \
    { execution_unit_0/register_file_0/clock_gate_r13 omsp_clock_gate_0 } \
    { execution_unit_0/register_file_0/clock_gate_r14 omsp_clock_gate_0 } \
    { execution_unit_0/register_file_0/clock_gate_r15 omsp_clock_gate_0 } \
    { clock_module_0/and_cpuoff_mclk_en omsp_and_gate_0 } \
    { clock_module_0/and_dco_dis1 omsp_and_gate_0 } \
    { clock_module_0/and_dco_dis2 omsp_and_gate_0 } \
    { clock_module_0/and_dco_dis3 omsp_and_gate_0 } \
    { clock_module_0/and_dco_dis4 omsp_and_gate_0 } \
    { clock_module_0/and_dco_dis5 omsp_and_gate_0 } \
    { clock_module_0/and_dco_mclk_wkup omsp_and_gate_0 } \
    { clock_module_0/and_dco_en_wkup omsp_and_gate_0 } \
    { clock_module_0/and_dco_wkup omsp_and_gate_0 } \
    { clock_module_0/and_lfxt_dis1 omsp_and_gate_0 } \
    { clock_module_0/and_lfxt_dis2 omsp_and_gate_0 } \
    { clock_module_0/and_lfxt_dis3 omsp_and_gate_0 } \
    { clock_module_0/and_lfxt_dis4 omsp_and_gate_0 } \
    { clock_module_0/and_lfxt_dis5 omsp_and_gate_0 } \
    { clock_module_0/and_lfxt_mclk_wkup omsp_and_gate_0 } \
    { clock_module_0/and_lfxt_en_wkup omsp_and_gate_0 } \
    { clock_module_0/and_lfxt_wkup omsp_and_gate_0 } \
    { frontend_0/and_mirq_wkup omsp_and_gate_0 } \
    { frontend_0/and_mclk_wkup omsp_and_gate_0 } \
    { sfr_0/and_nmi_wkup omsp_and_gate_0 } \
    { watchdog_0/and_wdt_wkup omsp_and_gate_0 } \
    { clock_module_0/scan_mux_dco_wkup omsp_scan_mux_0 } \
    { clock_module_0/scan_mux_dco_wkup_clear omsp_scan_mux_0 } \
    { clock_module_0/scan_mux_lfxt_wkup omsp_scan_mux_0 } \
    { clock_module_0/scan_mux_lfxt_wkup_clear omsp_scan_mux_0 } \
    { clock_module_0/scan_mux_puc_lfxt omsp_scan_mux_0 } \
    { clock_module_0/scan_mux_puc_sm omsp_scan_mux_0 } \
    { clock_module_0/scan_mux_por omsp_scan_mux_0 } \
    { clock_module_0/scan_mux_dbg_rst omsp_scan_mux_0 } \
    { clock_module_0/scan_mux_puc_rst_a omsp_scan_mux_0 } \
    { clock_module_0/scan_mux_puc_rst omsp_scan_mux_0 } \
    { watchdog_0/scan_mux_wdt_rst omsp_scan_mux_0 } \
    { sfr_0/wakeup_cell_nmi/scan_mux_rst omsp_scan_mux_0 } \
    { sfr_0/wakeup_cell_nmi/scan_mux_clk omsp_scan_mux_0 } \
    { watchdog_0/wakeup_cell_wdog/scan_mux_rst omsp_scan_mux_0 } \
    { watchdog_0/wakeup_cell_wdog/scan_mux_clk omsp_scan_mux_0 } \
    { sfr_0/wakeup_cell_nmi omsp_wakeup_cell_0 } \
    { watchdog_0/wakeup_cell_wdog omsp_wakeup_cell_0 } \
    { clock_module_0/sync_reset_por omsp_sync_reset_0 } \
    { watchdog_0/sync_reset_por omsp_sync_reset_0 } \
    { clock_module_0/clock_mux_mclk omsp_clock_mux_0 } \
    { clock_module_0/clock_mux_smclk omsp_clock_mux_0 } \
    { watchdog_0/clock_mux_watchdog omsp_clock_mux_0 } } 



guide_change_names \
  -design { omsp_register_file } \
  { { cell add_122 add_x_1 } } 

guide_reg_merging \
  -design { omsp_register_file } \
  -from { r2_reg[10] r2_reg[11] r2_reg[12] r2_reg[13] r2_reg[14] r2_reg[15] } \
  -to { r2_reg[9] } 



guide_change_names \
  -design { omsp_frontend } \
  { { cell ne_233 ne_x_1 } } 

guide_change_names \
  -design { omsp_frontend } \
  { { cell add_361 add_x_6 } } 

guide_change_names \
  -design { omsp_frontend } \
  { { cell add_410 add_x_8 } } 

guide_change_names \
  -design { omsp_frontend } \
  { { cell add_762 add_x_39 } } 

guide_reg_merging \
  -design { omsp_frontend } \
  -from { inst_ad_reg[3] inst_ad_reg[5] inst_ad_reg[7] } \
  -to { inst_ad_reg[2] } 

guide_reg_merging \
  -design { omsp_frontend } \
  -from { inst_jmp_bin_reg[0] } \
  -to { inst_src_bin_reg[2] } 

guide_reg_merging \
  -design { omsp_frontend } \
  -from { inst_jmp_bin_reg[1] } \
  -to { inst_src_bin_reg[3] } 

guide_inv_push \
  -design { omsp_frontend } \
  -register { inst_type_reg[1] } 

guide_inv_push \
  -design { omsp_frontend } \
  -register { inst_type_reg[0] } 

guide_inv_push \
  -design { omsp_frontend } \
  -register { inst_jmp_bin_reg[2] } 

guide_inv_push \
  -design { omsp_frontend } \
  -register { inst_dest_bin_reg[1] } 

guide_inv_push \
  -design { omsp_frontend } \
  -register { inst_src_bin_reg[1] } 

guide_inv_push \
  -design { omsp_frontend } \
  -register { inst_src_bin_reg[0] } 

guide_inv_push \
  -design { omsp_frontend } \
  -register { inst_alu_reg[1] } 

guide_change_names \
  -design { omsp_clock_module } \
  { { cell add_596_S2 add_x_1 } } 

guide_change_names \
  -design { omsp_clock_module } \
  { { cell add_691_S2 add_x_3 } } 

guide_change_names \
  -design { omsp_clock_module } \
  { { cell add_833_S2 add_x_5 } } 

guide_reg_merging \
  -design { omsp_clock_module } \
  -from { bcsctl2_reg[6] } \
  -to { bcsctl2_reg[0] } 

guide_reg_merging \
  -design { omsp_clock_module } \
  -from { bcsctl1_reg[1] bcsctl1_reg[2] bcsctl1_reg[3] bcsctl1_reg[6] bcsctl1_reg[7] } \
  -to { bcsctl1_reg[0] } 

guide_inv_push \
  -design { omsp_clock_module } \
  -register { divax_s_reg[1] } 

guide_inv_push \
  -design { omsp_clock_module } \
  -register { divax_ss_reg[1] } 

guide_inv_push \
  -design { omsp_clock_module } \
  -register { divax_s_reg[0] } 

guide_inv_push \
  -design { omsp_clock_module } \
  -register { divax_ss_reg[0] } 

guide_inv_push \
  -design { omsp_clock_module } \
  -register { divsx_s_reg[1] } 

guide_inv_push \
  -design { omsp_clock_module } \
  -register { divsx_ss_reg[1] } 

guide_inv_push \
  -design { omsp_clock_module } \
  -register { divsx_s_reg[0] } 

guide_inv_push \
  -design { omsp_clock_module } \
  -register { divsx_ss_reg[0] } 



guide_inv_push \
  -design { omsp_execution_unit } \
  -register { mdb_in_buf_en_reg } 

guide_uniquify \
  -design { omsp_divider_16b } \
  { { U1 omsp_divider_16b_DW_div_J3_0 } } 

guide_multiplier \
  -design { omsp_divider_16b } \
  -instance { U1 } \
  -arch { cla } 



guide_change_names \
  -design { omsp_dbg } \
  { { cell add_416 add_x_7 } } 

guide_change_names \
  -design { omsp_dbg } \
  { { cell add_429 add_x_9 } } 

guide_merge \
  -design { omsp_alu } \
  -datapath { DP_OP_67J4_124_3245 } \
  -input { 17 I1 } \
  -input { 16 I2 } \
  -input { 1 I3 } \
  -output { 17 O1 } \
  -output { 17 O2 } \
  -pre_resource { { 17 } add_171 = ADD { { I1 } { I2 ZERO 17 } } } \
  -pre_resource { { 17 } add_180 = ADD { { add_171.out.1 } { I3 ZERO 17 } } } \
  -pre_assign { O1 = { add_171.out.1 } } \
  -pre_assign { O2 = { add_180.out.1 } } 

guide_replace \
  -origin { ExTra_tree } \
  -design { omsp_alu } \
  -input { 4 src35 } \
  -input { 4 src36 } \
  -input { 1 src38 } \
  -output { 5 O1 } \
  -pre_resource { { 5 } add_100_C185 = ADD { { src35 ZERO 5 } { src36 ZERO 5 } } } \
  -pre_resource { { 5 } add_100_2_C185 = ADD { { add_100_C185.out.1 ANY 5 } { src38 ZERO 5 } } } \
  -pre_assign { O1 = { add_100_2_C185.out.1 ANY 5 } } \
  -post_resource { { 5 } EXTRA_ADD_63_1 = ADD { { src35 ZERO 5 } { src36 ZERO 5 } } } \
  -post_resource { { 5 } EXTRA_ADD_63 = ADD { { EXTRA_ADD_63_1.out.1 ANY 5 } { src38 ZERO 5 } } } \
  -post_assign { O1 = { EXTRA_ADD_63.out.1 ANY 5 } } 

guide_merge \
  -design { omsp_alu } \
  -datapath { DP_OP_68J4_125_7159 } \
  -input { 4 I1 } \
  -input { 4 I2 } \
  -input { 1 I3 } \
  -input { 3 I4 } \
  -output { 1 O1 } \
  -output { 5 O2 } \
  -pre_resource { { 5 } EXTRA_ADD_63_1 = ADD { { I1 ZERO 5 } { I2 ZERO 5 } } } \
  -pre_resource { { 5 } EXTRA_ADD_63 = ADD { { EXTRA_ADD_63_1.out.1 } { I3 ZERO 5 } } } \
  -pre_resource { { 1 } lt_101_C185 = LT { { EXTRA_ADD_63.out.1 ZERO 5 } { U`b01010 } } } \
  -pre_resource { { 5 } add_102_C185_aco = ADD { { EXTRA_ADD_63.out.1 } { I4 ZERO 5 } } } \
  -pre_assign { O1 = { lt_101_C185.out.1 } } \
  -pre_assign { O2 = { add_102_C185_aco.out.1 } } 

guide_replace \
  -origin { ExTra_tree } \
  -design { omsp_alu } \
  -input { 4 src41 } \
  -input { 4 src42 } \
  -input { 1 src43 } \
  -output { 5 O1 } \
  -pre_resource { { 5 } add_100_C186 = ADD { { src41 ZERO 5 } { src42 ZERO 5 } } } \
  -pre_resource { { 5 } add_100_2_C186 = ADD { { add_100_C186.out.1 ANY 5 } { src43 ZERO 5 } } } \
  -pre_assign { O1 = { add_100_2_C186.out.1 ANY 5 } } \
  -post_resource { { 5 } EXTRA_ADD_64_1 = ADD { { src41 ZERO 5 } { src42 ZERO 5 } } } \
  -post_resource { { 5 } EXTRA_ADD_64 = ADD { { EXTRA_ADD_64_1.out.1 ANY 5 } { src43 ZERO 5 } } } \
  -post_assign { O1 = { EXTRA_ADD_64.out.1 ANY 5 } } 

guide_merge \
  -design { omsp_alu } \
  -datapath { DP_OP_69J4_126_7159 } \
  -input { 4 I1 } \
  -input { 4 I2 } \
  -input { 1 I3 } \
  -input { 3 I4 } \
  -output { 1 O1 } \
  -output { 5 O2 } \
  -pre_resource { { 5 } EXTRA_ADD_64_1 = ADD { { I1 ZERO 5 } { I2 ZERO 5 } } } \
  -pre_resource { { 5 } EXTRA_ADD_64 = ADD { { EXTRA_ADD_64_1.out.1 } { I3 ZERO 5 } } } \
  -pre_resource { { 1 } lt_101_C186 = LT { { EXTRA_ADD_64.out.1 ZERO 5 } { U`b01010 } } } \
  -pre_resource { { 5 } add_102_C186_aco = ADD { { EXTRA_ADD_64.out.1 } { I4 ZERO 5 } } } \
  -pre_assign { O1 = { lt_101_C186.out.1 } } \
  -pre_assign { O2 = { add_102_C186_aco.out.1 } } 

guide_replace \
  -origin { ExTra_tree } \
  -design { omsp_alu } \
  -input { 4 src46 } \
  -input { 4 src47 } \
  -input { 1 src48 } \
  -output { 5 O1 } \
  -pre_resource { { 5 } add_100_C187 = ADD { { src46 ZERO 5 } { src47 ZERO 5 } } } \
  -pre_resource { { 5 } add_100_2_C187 = ADD { { add_100_C187.out.1 ANY 5 } { src48 ZERO 5 } } } \
  -pre_assign { O1 = { add_100_2_C187.out.1 ANY 5 } } \
  -post_resource { { 5 } EXTRA_ADD_65_1 = ADD { { src46 ZERO 5 } { src47 ZERO 5 } } } \
  -post_resource { { 5 } EXTRA_ADD_65 = ADD { { EXTRA_ADD_65_1.out.1 ANY 5 } { src48 ZERO 5 } } } \
  -post_assign { O1 = { EXTRA_ADD_65.out.1 ANY 5 } } 

guide_merge \
  -design { omsp_alu } \
  -datapath { DP_OP_70J4_127_7159 } \
  -input { 4 I1 } \
  -input { 4 I2 } \
  -input { 1 I3 } \
  -input { 3 I4 } \
  -output { 1 O1 } \
  -output { 5 O2 } \
  -pre_resource { { 5 } EXTRA_ADD_65_1 = ADD { { I1 ZERO 5 } { I2 ZERO 5 } } } \
  -pre_resource { { 5 } EXTRA_ADD_65 = ADD { { EXTRA_ADD_65_1.out.1 } { I3 ZERO 5 } } } \
  -pre_resource { { 1 } lt_101_C187 = LT { { EXTRA_ADD_65.out.1 ZERO 5 } { U`b01010 } } } \
  -pre_resource { { 5 } add_102_C187_aco = ADD { { EXTRA_ADD_65.out.1 } { I4 ZERO 5 } } } \
  -pre_assign { O1 = { lt_101_C187.out.1 } } \
  -pre_assign { O2 = { add_102_C187_aco.out.1 } } 

guide_replace \
  -origin { ExTra_tree } \
  -design { omsp_alu } \
  -input { 4 src50 } \
  -input { 4 src51 } \
  -input { 1 src52 } \
  -output { 5 O1 } \
  -pre_resource { { 5 } add_100_C188 = ADD { { src50 ZERO 5 } { src51 ZERO 5 } } } \
  -pre_resource { { 5 } add_100_2_C188 = ADD { { add_100_C188.out.1 ANY 5 } { src52 ZERO 5 } } } \
  -pre_assign { O1 = { add_100_2_C188.out.1 ANY 5 } } \
  -post_resource { { 5 } EXTRA_ADD_66_1 = ADD { { src50 ZERO 5 } { src51 ZERO 5 } } } \
  -post_resource { { 5 } EXTRA_ADD_66 = ADD { { EXTRA_ADD_66_1.out.1 ANY 5 } { src52 ZERO 5 } } } \
  -post_assign { O1 = { EXTRA_ADD_66.out.1 ANY 5 } } 

guide_merge \
  -design { omsp_alu } \
  -datapath { DP_OP_71J4_128_7159 } \
  -input { 4 I1 } \
  -input { 4 I2 } \
  -input { 1 I3 } \
  -input { 3 I4 } \
  -output { 1 O1 } \
  -output { 5 O2 } \
  -pre_resource { { 5 } EXTRA_ADD_66_1 = ADD { { I1 ZERO 5 } { I2 ZERO 5 } } } \
  -pre_resource { { 5 } EXTRA_ADD_66 = ADD { { EXTRA_ADD_66_1.out.1 } { I3 ZERO 5 } } } \
  -pre_resource { { 1 } lt_101_C188 = LT { { EXTRA_ADD_66.out.1 ZERO 5 } { U`b01010 } } } \
  -pre_resource { { 5 } add_102_C188_aco = ADD { { EXTRA_ADD_66.out.1 } { I4 ZERO 5 } } } \
  -pre_assign { O1 = { lt_101_C188.out.1 } } \
  -pre_assign { O2 = { add_102_C188_aco.out.1 } } 

guide_uniquify \
  -design { omsp_alu } \
  { { DP_OP_71J4_128_7159 omsp_alu_DP_OP_71J4_128_7159_J4_0 } } 

guide_uniquify \
  -design { omsp_alu } \
  { { DP_OP_70J4_127_7159 omsp_alu_DP_OP_70J4_127_7159_J4_0 } } 

guide_uniquify \
  -design { omsp_alu } \
  { { DP_OP_69J4_126_7159 omsp_alu_DP_OP_69J4_126_7159_J4_0 } } 

guide_uniquify \
  -design { omsp_alu } \
  { { DP_OP_68J4_125_7159 omsp_alu_DP_OP_68J4_125_7159_J4_0 } } 

guide_uniquify \
  -design { omsp_alu } \
  { { DP_OP_67J4_124_3245 omsp_alu_DP_OP_67J4_124_3245_J4_0 } } 

guide_boundary_netlist \
  -file { netlists/S1/J4/dw-1 } \
  { saed90nm_typ_ht } 

guide_replace \
  -origin { Gensh } \
  -body { omsp_alu_DP_OP_71J4_128_7159_J4_0 } \
  -input { unsigned 4 I1 bin } \
  -input { unsigned 4 I2 bin } \
  -input { unsigned 1 I3 bin } \
  -input { unsigned 3 I4 bin } \
  -output { 1 O1 bin } \
  -output { 5 O2 bin } \
  -pre_resource { { 5 } OP0 = ADD { { I1 ZERO 5 } { I2 ZERO 5 } } } \
  -pre_resource { { 5 } OP1 = ADD { { OP0.out.1 ZERO 5 } { I3 ZERO 5 } } } \
  -pre_resource { { 1 } OP2 = LT { { OP1.out.1 ZERO 5 } { U`b1010 ZERO 5 } } } \
  -pre_resource { { 5 } OP3 = ADD { { OP1.out.1 ZERO 5 } { I4 ZERO 5 } } } \
  -pre_assign { O1 = { OP2.out.1 ZERO 1 } } \
  -pre_assign { O2 = { OP3.out.1 ZERO 5 } } \
  -post_resource { { 5 } OP1 = SOP { { { I2 ZERO 5 } } { { I1 ZERO 5 } } { { I3 ZERO 5 } } } } \
  -post_resource { { 1 } OP2 = LT { { OP1.out.1 ZERO 5 } { U`b1010 ZERO 5 } } } \
  -post_resource { { 5 } OP3 = ADD { { OP1.out.1 ZERO 5 } { I4 ZERO 5 } } } \
  -post_assign { O1 = { OP2.out.1 ZERO 1 } } \
  -post_assign { O2 = { OP3.out.1 ZERO 5 } } 

guide_boundary \
  -body { omsp_alu_DP_OP_71J4_128_7159_J4_0 } \
  -operand { I1 bin 4 } \
  -operand { I2 bin 4 } \
  -operand { I3 bin 1 } \
  -operand { I4 bin 3 } \
  -operand { OP2.out.1 bin 1 } \
  -operand { OP3.out.1 bin 5 } \
  -operand { OP1.out.1 bin 5 } \
  -column { I1 0 { I1[0] } } \
  -column { I1 1 { I1[1] } } \
  -column { I1 2 { I1[2] } } \
  -column { I1 3 { I1[3] } } \
  -column { I2 0 { I2[0] } } \
  -column { I2 1 { I2[1] } } \
  -column { I2 2 { I2[2] } } \
  -column { I2 3 { I2[3] } } \
  -column { I3 0 { I3 } } \
  -column { I4 0 { 0 } } \
  -column { I4 1 { I4[1] } } \
  -column { I4 2 { I4[1] } } \
  -column { OP2.out.1 0 { O1 } } \
  -column { OP3.out.1 0 { O2[0] } } \
  -column { OP3.out.1 1 { O2[1] } } \
  -column { OP3.out.1 2 { O2[2] } } \
  -column { OP3.out.1 3 { O2[3] } } \
  -column { OP3.out.1 4 { O2[4] } } \
  -column { OP1.out.1 0 { O2[0] } } \
  -column { OP1.out.1 1 { n41 } } \
  -column { OP1.out.1 2 { n42 } } \
  -column { OP1.out.1 3 { n43 } } \
  -column { OP1.out.1 4 { n44 } } \
  -resource { OP1 { I2 I1 I3 } { OP1.out.1 } } \
  -resource { OP2 { OP1.out.1 } { OP2.out.1 } } \
  -resource { OP3 { OP1.out.1 I4 } { OP3.out.1 } } 

guide_constraints \
  -body { omsp_alu_DP_OP_71J4_128_7159_J4_0 } \
  -const0 \
  { I4[0] } \
  -equivalent \
  { { I4[1]  I4[2] } } 

guide_replace \
  -origin { Gensh } \
  -body { omsp_alu_DP_OP_70J4_127_7159_J4_0 } \
  -input { unsigned 4 I1 bin } \
  -input { unsigned 4 I2 bin } \
  -input { unsigned 1 I3 bin } \
  -input { unsigned 3 I4 bin } \
  -output { 1 O1 bin } \
  -output { 5 O2 bin } \
  -pre_resource { { 5 } OP4 = ADD { { I1 ZERO 5 } { I2 ZERO 5 } } } \
  -pre_resource { { 5 } OP5 = ADD { { OP4.out.1 ZERO 5 } { I3 ZERO 5 } } } \
  -pre_resource { { 1 } OP6 = LT { { OP5.out.1 ZERO 5 } { U`b1010 ZERO 5 } } } \
  -pre_resource { { 5 } OP7 = ADD { { OP5.out.1 ZERO 5 } { I4 ZERO 5 } } } \
  -pre_assign { O1 = { OP6.out.1 ZERO 1 } } \
  -pre_assign { O2 = { OP7.out.1 ZERO 5 } } \
  -post_resource { { 5 } OP5 = SOP { { { I2 ZERO 5 } } { { I1 ZERO 5 } } { { I3 ZERO 5 } } } } \
  -post_resource { { 1 } OP6 = LT { { OP5.out.1 ZERO 5 } { U`b1010 ZERO 5 } } } \
  -post_resource { { 5 } OP7 = ADD { { OP5.out.1 ZERO 5 } { I4 ZERO 5 } } } \
  -post_assign { O1 = { OP6.out.1 ZERO 1 } } \
  -post_assign { O2 = { OP7.out.1 ZERO 5 } } 

guide_boundary \
  -body { omsp_alu_DP_OP_70J4_127_7159_J4_0 } \
  -operand { I1 bin 4 } \
  -operand { I2 bin 4 } \
  -operand { I3 bin 1 } \
  -operand { I4 bin 3 } \
  -operand { OP6.out.1 bin 1 } \
  -operand { OP7.out.1 bin 5 } \
  -operand { OP5.out.1 bin 5 } \
  -column { I1 0 { I1[0] } } \
  -column { I1 1 { I1[1] } } \
  -column { I1 2 { I1[2] } } \
  -column { I1 3 { I1[3] } } \
  -column { I2 0 { I2[0] } } \
  -column { I2 1 { I2[1] } } \
  -column { I2 2 { I2[2] } } \
  -column { I2 3 { I2[3] } } \
  -column { I3 0 { I3 } } \
  -column { I4 0 { 0 } } \
  -column { I4 1 { I4[1] } } \
  -column { I4 2 { I4[1] } } \
  -column { OP6.out.1 0 { O1 } } \
  -column { OP7.out.1 0 { O2[0] } } \
  -column { OP7.out.1 1 { O2[1] } } \
  -column { OP7.out.1 2 { O2[2] } } \
  -column { OP7.out.1 3 { O2[3] } } \
  -column { OP7.out.1 4 { O2[4] } } \
  -column { OP5.out.1 0 { O2[0] } } \
  -column { OP5.out.1 1 { n41 } } \
  -column { OP5.out.1 2 { n42 } } \
  -column { OP5.out.1 3 { n43 } } \
  -column { OP5.out.1 4 { n44 } } \
  -resource { OP5 { I2 I1 I3 } { OP5.out.1 } } \
  -resource { OP6 { OP5.out.1 } { OP6.out.1 } } \
  -resource { OP7 { OP5.out.1 I4 } { OP7.out.1 } } 

guide_constraints \
  -body { omsp_alu_DP_OP_70J4_127_7159_J4_0 } \
  -const0 \
  { I4[0] } \
  -equivalent \
  { { I4[1]  I4[2] } } 

guide_replace \
  -origin { Gensh } \
  -body { omsp_alu_DP_OP_69J4_126_7159_J4_0 } \
  -input { unsigned 4 I1 bin } \
  -input { unsigned 4 I2 bin } \
  -input { unsigned 1 I3 bin } \
  -input { unsigned 3 I4 bin } \
  -output { 1 O1 bin } \
  -output { 5 O2 bin } \
  -pre_resource { { 5 } OP8 = ADD { { I1 ZERO 5 } { I2 ZERO 5 } } } \
  -pre_resource { { 5 } OP9 = ADD { { OP8.out.1 ZERO 5 } { I3 ZERO 5 } } } \
  -pre_resource { { 1 } OP10 = LT { { OP9.out.1 ZERO 5 } { U`b1010 ZERO 5 } } } \
  -pre_resource { { 5 } OP11 = ADD { { OP9.out.1 ZERO 5 } { I4 ZERO 5 } } } \
  -pre_assign { O1 = { OP10.out.1 ZERO 1 } } \
  -pre_assign { O2 = { OP11.out.1 ZERO 5 } } \
  -post_resource { { 5 } OP9 = SOP { { { I2 ZERO 5 } } { { I1 ZERO 5 } } { { I3 ZERO 5 } } } } \
  -post_resource { { 1 } OP10 = LT { { OP9.out.1 ZERO 5 } { U`b1010 ZERO 5 } } } \
  -post_resource { { 5 } OP11 = ADD { { OP9.out.1 ZERO 5 } { I4 ZERO 5 } } } \
  -post_assign { O1 = { OP10.out.1 ZERO 1 } } \
  -post_assign { O2 = { OP11.out.1 ZERO 5 } } 

guide_boundary \
  -body { omsp_alu_DP_OP_69J4_126_7159_J4_0 } \
  -operand { I1 bin 4 } \
  -operand { I2 bin 4 } \
  -operand { I3 bin 1 } \
  -operand { I4 bin 3 } \
  -operand { OP10.out.1 bin 1 } \
  -operand { OP11.out.1 bin 5 } \
  -operand { OP9.out.1 bin 5 } \
  -column { I1 0 { I1[0] } } \
  -column { I1 1 { I1[1] } } \
  -column { I1 2 { I1[2] } } \
  -column { I1 3 { I1[3] } } \
  -column { I2 0 { I2[0] } } \
  -column { I2 1 { I2[1] } } \
  -column { I2 2 { I2[2] } } \
  -column { I2 3 { I2[3] } } \
  -column { I3 0 { I3 } } \
  -column { I4 0 { 0 } } \
  -column { I4 1 { I4[1] } } \
  -column { I4 2 { I4[1] } } \
  -column { OP10.out.1 0 { O1 } } \
  -column { OP11.out.1 0 { O2[0] } } \
  -column { OP11.out.1 1 { O2[1] } } \
  -column { OP11.out.1 2 { O2[2] } } \
  -column { OP11.out.1 3 { O2[3] } } \
  -column { OP11.out.1 4 { O2[4] } } \
  -column { OP9.out.1 0 { O2[0] } } \
  -column { OP9.out.1 1 { n41 } } \
  -column { OP9.out.1 2 { n42 } } \
  -column { OP9.out.1 3 { n43 } } \
  -column { OP9.out.1 4 { n44 } } \
  -resource { OP9 { I2 I1 I3 } { OP9.out.1 } } \
  -resource { OP10 { OP9.out.1 } { OP10.out.1 } } \
  -resource { OP11 { OP9.out.1 I4 } { OP11.out.1 } } 

guide_constraints \
  -body { omsp_alu_DP_OP_69J4_126_7159_J4_0 } \
  -const0 \
  { I4[0] } \
  -equivalent \
  { { I4[1]  I4[2] } } 

guide_replace \
  -origin { Gensh } \
  -body { omsp_alu_DP_OP_68J4_125_7159_J4_0 } \
  -input { unsigned 4 I1 bin } \
  -input { unsigned 4 I2 bin } \
  -input { unsigned 1 I3 bin } \
  -input { unsigned 3 I4 bin } \
  -output { 1 O1 bin } \
  -output { 5 O2 bin } \
  -pre_resource { { 5 } OP12 = ADD { { I1 ZERO 5 } { I2 ZERO 5 } } } \
  -pre_resource { { 5 } OP13 = ADD { { OP12.out.1 ZERO 5 } { I3 ZERO 5 } } } \
  -pre_resource { { 1 } OP14 = LT { { OP13.out.1 ZERO 5 } { U`b1010 ZERO 5 } } } \
  -pre_resource { { 5 } OP15 = ADD { { OP13.out.1 ZERO 5 } { I4 ZERO 5 } } } \
  -pre_assign { O1 = { OP14.out.1 ZERO 1 } } \
  -pre_assign { O2 = { OP15.out.1 ZERO 5 } } \
  -post_resource { { 5 } OP13 = SOP { { { I2 ZERO 5 } } { { I1 ZERO 5 } } { { I3 ZERO 5 } } } } \
  -post_resource { { 1 } OP14 = LT { { OP13.out.1 ZERO 5 } { U`b1010 ZERO 5 } } } \
  -post_resource { { 5 } OP15 = ADD { { OP13.out.1 ZERO 5 } { I4 ZERO 5 } } } \
  -post_assign { O1 = { OP14.out.1 ZERO 1 } } \
  -post_assign { O2 = { OP15.out.1 ZERO 5 } } 

guide_boundary \
  -body { omsp_alu_DP_OP_68J4_125_7159_J4_0 } \
  -operand { I1 bin 4 } \
  -operand { I2 bin 4 } \
  -operand { I3 bin 1 } \
  -operand { I4 bin 3 } \
  -operand { OP14.out.1 bin 1 } \
  -operand { OP15.out.1 bin 5 } \
  -operand { OP13.out.1 bin 5 } \
  -column { I1 0 { I1[0] } } \
  -column { I1 1 { I1[1] } } \
  -column { I1 2 { I1[2] } } \
  -column { I1 3 { I1[3] } } \
  -column { I2 0 { I2[0] } } \
  -column { I2 1 { I2[1] } } \
  -column { I2 2 { I2[2] } } \
  -column { I2 3 { I2[3] } } \
  -column { I3 0 { I3 } } \
  -column { I4 0 { 0 } } \
  -column { I4 1 { I4[1] } } \
  -column { I4 2 { I4[1] } } \
  -column { OP14.out.1 0 { O1 } } \
  -column { OP15.out.1 0 { O2[0] } } \
  -column { OP15.out.1 1 { O2[1] } } \
  -column { OP15.out.1 2 { O2[2] } } \
  -column { OP15.out.1 3 { O2[3] } } \
  -column { OP15.out.1 4 { O2[4] } } \
  -column { OP13.out.1 0 { O2[0] } } \
  -column { OP13.out.1 1 { n41 } } \
  -column { OP13.out.1 2 { n42 } } \
  -column { OP13.out.1 3 { n43 } } \
  -column { OP13.out.1 4 { n44 } } \
  -resource { OP13 { I2 I1 I3 } { OP13.out.1 } } \
  -resource { OP14 { OP13.out.1 } { OP14.out.1 } } \
  -resource { OP15 { OP13.out.1 I4 } { OP15.out.1 } } 

guide_constraints \
  -body { omsp_alu_DP_OP_68J4_125_7159_J4_0 } \
  -const0 \
  { I4[0] } \
  -equivalent \
  { { I4[1]  I4[2] } } 

guide_replace \
  -origin { Gensh } \
  -body { omsp_alu_DP_OP_67J4_124_3245_J4_0 } \
  -input { unsigned 17 I1 bin } \
  -input { unsigned 16 I2 bin } \
  -input { unsigned 1 I3 bin } \
  -output { 17 O1 bin } \
  -output { 17 O2 bin } \
  -pre_resource { { 17 } OP16 = ADD { { I1 ZERO 17 } { I2 ZERO 17 } } } \
  -pre_resource { { 17 } OP17 = ADD { { OP16.out.1 ZERO 17 } { I3 ZERO 17 } } } \
  -pre_assign { O1 = { OP16.out.1 ZERO 17 } } \
  -pre_assign { O2 = { OP17.out.1 ZERO 17 } } \
  -post_resource { { 17 } OP16 = ADD { { I1 ZERO 17 } { I2 ZERO 17 } } } \
  -post_resource { { 17 } OP17 = ADD { { OP16.out.1 ZERO 17 } { I3 ZERO 17 } } } \
  -post_assign { O1 = { OP16.out.1 ZERO 17 } } \
  -post_assign { O2 = { OP17.out.1 ZERO 17 } } 

guide_boundary \
  -body { omsp_alu_DP_OP_67J4_124_3245_J4_0 } \
  -operand { I1 bin 17 } \
  -operand { I2 bin 16 } \
  -operand { I3 bin 1 } \
  -operand { OP16.out.1 bin 17 } \
  -operand { OP17.out.1 bin 17 } \
  -column { I1 0 { I1[0] } } \
  -column { I1 1 { I1[1] } } \
  -column { I1 2 { I1[2] } } \
  -column { I1 3 { I1[3] } } \
  -column { I1 4 { I1[4] } } \
  -column { I1 5 { I1[5] } } \
  -column { I1 6 { I1[6] } } \
  -column { I1 7 { I1[7] } } \
  -column { I1 8 { I1[8] } } \
  -column { I1 9 { I1[9] } } \
  -column { I1 10 { I1[10] } } \
  -column { I1 11 { I1[11] } } \
  -column { I1 12 { I1[12] } } \
  -column { I1 13 { I1[13] } } \
  -column { I1 14 { I1[14] } } \
  -column { I1 15 { I1[15] } } \
  -column { I1 16 { 0 } } \
  -column { I2 0 { I2[0] } } \
  -column { I2 1 { I2[1] } } \
  -column { I2 2 { I2[2] } } \
  -column { I2 3 { I2[3] } } \
  -column { I2 4 { I2[4] } } \
  -column { I2 5 { I2[5] } } \
  -column { I2 6 { I2[6] } } \
  -column { I2 7 { I2[7] } } \
  -column { I2 8 { I2[8] } } \
  -column { I2 9 { I2[9] } } \
  -column { I2 10 { I2[10] } } \
  -column { I2 11 { I2[11] } } \
  -column { I2 12 { I2[12] } } \
  -column { I2 13 { I2[13] } } \
  -column { I2 14 { I2[14] } } \
  -column { I2 15 { I2[15] } } \
  -column { I3 0 { I3 } } \
  -column { OP16.out.1 0 { O1[0] } } \
  -column { OP16.out.1 1 { O1[1] } } \
  -column { OP16.out.1 2 { O1[2] } } \
  -column { OP16.out.1 3 { O1[3] } } \
  -column { OP16.out.1 4 { O1[4] } } \
  -column { OP16.out.1 5 { O1[5] } } \
  -column { OP16.out.1 6 { O1[6] } } \
  -column { OP16.out.1 7 { O1[7] } } \
  -column { OP16.out.1 8 { O1[8] } } \
  -column { OP16.out.1 9 { O1[9] } } \
  -column { OP16.out.1 10 { O1[10] } } \
  -column { OP16.out.1 11 { O1[11] } } \
  -column { OP16.out.1 12 { O1[12] } } \
  -column { OP16.out.1 13 { O1[13] } } \
  -column { OP16.out.1 14 { O1[14] } } \
  -column { OP16.out.1 15 { O1[15] } } \
  -column { OP16.out.1 16 { O1[16] } } \
  -column { OP17.out.1 0 { O2[0] } } \
  -column { OP17.out.1 1 { O2[1] } } \
  -column { OP17.out.1 2 { O2[2] } } \
  -column { OP17.out.1 3 { O2[3] } } \
  -column { OP17.out.1 4 { O2[4] } } \
  -column { OP17.out.1 5 { O2[5] } } \
  -column { OP17.out.1 6 { O2[6] } } \
  -column { OP17.out.1 7 { O2[7] } } \
  -column { OP17.out.1 8 { O2[8] } } \
  -column { OP17.out.1 9 { O2[9] } } \
  -column { OP17.out.1 10 { O2[10] } } \
  -column { OP17.out.1 11 { O2[11] } } \
  -column { OP17.out.1 12 { O2[12] } } \
  -column { OP17.out.1 13 { O2[13] } } \
  -column { OP17.out.1 14 { O2[14] } } \
  -column { OP17.out.1 15 { O2[15] } } \
  -column { OP17.out.1 16 { O2[16] } } \
  -resource { OP16 { I1 I2 } { OP16.out.1 } } \
  -resource { OP17 { OP16.out.1 I3 } { OP17.out.1 } } 

guide_constraints \
  -body { omsp_alu_DP_OP_67J4_124_3245_J4_0 } \
  -const0 \
  { I1[16] } 

guide_architecture_netlist \
  -file { netlists/S1/J4/dw-1 } \
  { saed90nm_typ_ht } 

guide_datapath \
  -design { omsp_alu } \
  -datapath { DP_OP_71J4_128_7159 } \
  -body { omsp_alu_DP_OP_71J4_128_7159_J4_0 } 

guide_datapath \
  -design { omsp_alu } \
  -datapath { DP_OP_70J4_127_7159 } \
  -body { omsp_alu_DP_OP_70J4_127_7159_J4_0 } 

guide_datapath \
  -design { omsp_alu } \
  -datapath { DP_OP_69J4_126_7159 } \
  -body { omsp_alu_DP_OP_69J4_126_7159_J4_0 } 

guide_datapath \
  -design { omsp_alu } \
  -datapath { DP_OP_68J4_125_7159 } \
  -body { omsp_alu_DP_OP_68J4_125_7159_J4_0 } 

guide_datapath \
  -design { omsp_alu } \
  -datapath { DP_OP_67J4_124_3245 } \
  -body { omsp_alu_DP_OP_67J4_124_3245_J4_0 } 

guide_change_names \
  -design { omsp_watchdog } \
  { { cell add_322 add_x_1 } } 

guide_inv_push \
  -design { omsp_watchdog } \
  -register { wdtisx_s_reg[0] } 

guide_inv_push \
  -design { omsp_watchdog } \
  -register { wdtisx_ss_reg[0] } 

guide_inv_push \
  -design { omsp_watchdog } \
  -register { wdtisx_s_reg[1] } 

guide_inv_push \
  -design { omsp_watchdog } \
  -register { wdtisx_ss_reg[1] } 

guide_inv_push \
  -design { omsp_watchdog } \
  -register { wdtqn_edge_reg_reg } 

guide_inv_push \
  -design { omsp_sync_cell_0 } \
  -register { data_sync_reg[1] } 



guide_change_names \
  -design { omsp_multiplier } \
  { { cell mult_393 mult_x_8 } } 

guide_change_names \
  -design { omsp_multiplier } \
  { { cell add_399 add_x_10 } } 

guide_uniquify \
  -design { omsp_multiplier } \
  { { mult_x_8 omsp_multiplier_DW_mult_tc_J5_0 } } 

guide_inv_push \
  -design { omsp_multiplier } \
  -register { cycle_reg[0] } 

guide_inv_push \
  -design { omsp_multiplier } \
  -register { cycle_reg[1] } 

guide_architecture_netlist \
  -file { netlists/S1/J5/dw-1 } \
  { saed90nm_typ_ht } 

guide_multiplier \
  -design { omsp_multiplier } \
  -instance { mult_x_8 } \
  -arch { apparch } \
  -body { omsp_multiplier_DW_mult_tc_J5_0 } 

guide_change_names \
  -design { omsp_dbg_uart } \
  { { cell add_215_S2 add_x_6 } } 

guide_change_names \
  -design { omsp_dbg_uart } \
  { { cell add_241_S2 add_x_8 } } 

guide_change_names \
  -design { omsp_dbg_uart } \
  { { cell add_247_S2 add_x_11 } } 

guide_change_names \
  -design { omsp_mem_backbone } \
  { { cell sub_143 RSOP_25_ADD_3 } } 

guide_change_names \
  -design { omsp_mem_backbone } \
  { { cell sub_138 RSOP_25_ADD_1 } } 

guide_change_names \
  -design { omsp_mem_backbone } \
  { { cell lt_136 lt_x_1 } } 

guide_change_names \
  -design { omsp_mem_backbone } \
  { { cell lt_141 lt_x_2 } } 

guide_change_names \
  -design { omsp_mem_backbone } \
  { { cell gte_158 gte_x_4 } } 

guide_change_names \
  -design { omsp_mem_backbone } \
  { { cell gte_162 gte_x_5 } } 

guide_change_names \
  -design { omsp_mem_backbone } \
  { { cell gte_166 gte_x_6 } } 

guide_inv_push \
  -design { omsp_mem_backbone } \
  -register { fe_pmem_cen_dly_reg } 

guide_inv_push \
  -design { omsp_mem_backbone } \
  -register { eu_mdb_in_sel_reg[1] } 



guide_uniquify \
  -design { openMSP430 } \
  { { dbg_0/dbg_uart_0/sync_cell_uart_rxd omsp_sync_cell_1 } \
    { watchdog_0/sync_cell_wdt_evt omsp_sync_cell_2 } \
    { watchdog_0/sync_cell_wdtcnt_incr omsp_sync_cell_3 } \
    { watchdog_0/sync_cell_wdtcnt_clr omsp_sync_cell_4 } \
    { sfr_0/sync_cell_nmi omsp_sync_cell_5 } \
    { clock_module_0/sync_cell_puc omsp_sync_cell_6 } \
    { clock_module_0/sync_cell_scg1 omsp_sync_cell_7 } \
    { clock_module_0/sync_cell_puc_sm omsp_sync_cell_8 } \
    { clock_module_0/sync_cell_oscoff omsp_sync_cell_9 } \
    { clock_module_0/sync_cell_puc_lfxt omsp_sync_cell_10 } \
    { clock_module_0/sync_cell_mclk_wkup omsp_sync_cell_11 } \
    { clock_module_0/sync_cell_cpu_sm_en omsp_sync_cell_12 } \
    { clock_module_0/sync_cell_cpu_aux_en omsp_sync_cell_13 } \
    { clock_module_0/sync_cell_lfxt_wkup omsp_sync_cell_14 } \
    { clock_module_0/sync_cell_lfxt_disable omsp_sync_cell_15 } \
    { clock_module_0/sync_cell_dco_wkup omsp_sync_cell_16 } \
    { watchdog_0/sync_reset_por omsp_sync_reset_1 } \
    { watchdog_0/wakeup_cell_wdog omsp_wakeup_cell_1 } \
    { watchdog_0/wakeup_cell_wdog/scan_mux_clk omsp_scan_mux_1 } \
    { watchdog_0/wakeup_cell_wdog/scan_mux_rst omsp_scan_mux_2 } \
    { sfr_0/wakeup_cell_nmi/scan_mux_clk omsp_scan_mux_3 } \
    { sfr_0/wakeup_cell_nmi/scan_mux_rst omsp_scan_mux_4 } \
    { watchdog_0/scan_mux_wdt_rst omsp_scan_mux_5 } \
    { clock_module_0/scan_mux_puc_rst omsp_scan_mux_6 } \
    { clock_module_0/scan_mux_puc_rst_a omsp_scan_mux_7 } \
    { clock_module_0/scan_mux_dbg_rst omsp_scan_mux_8 } \
    { clock_module_0/scan_mux_por omsp_scan_mux_9 } \
    { clock_module_0/scan_mux_puc_sm omsp_scan_mux_10 } \
    { clock_module_0/scan_mux_puc_lfxt omsp_scan_mux_11 } \
    { clock_module_0/scan_mux_lfxt_wkup_clear omsp_scan_mux_12 } \
    { clock_module_0/scan_mux_lfxt_wkup omsp_scan_mux_13 } \
    { clock_module_0/scan_mux_dco_wkup_clear omsp_scan_mux_14 } \
    { watchdog_0/clock_mux_watchdog omsp_clock_mux_1 } \
    { clock_module_0/clock_mux_smclk omsp_clock_mux_2 } \
    { execution_unit_0/register_file_0/clock_gate_r15 omsp_clock_gate_1 } \
    { execution_unit_0/register_file_0/clock_gate_r14 omsp_clock_gate_2 } \
    { execution_unit_0/register_file_0/clock_gate_r13 omsp_clock_gate_3 } \
    { execution_unit_0/register_file_0/clock_gate_r12 omsp_clock_gate_4 } \
    { execution_unit_0/register_file_0/clock_gate_r11 omsp_clock_gate_5 } \
    { execution_unit_0/register_file_0/clock_gate_r10 omsp_clock_gate_6 } \
    { execution_unit_0/register_file_0/clock_gate_r9 omsp_clock_gate_7 } \
    { execution_unit_0/register_file_0/clock_gate_r8 omsp_clock_gate_8 } \
    { execution_unit_0/register_file_0/clock_gate_r7 omsp_clock_gate_9 } \
    { execution_unit_0/register_file_0/clock_gate_r6 omsp_clock_gate_10 } \
    { execution_unit_0/register_file_0/clock_gate_r5 omsp_clock_gate_11 } \
    { execution_unit_0/register_file_0/clock_gate_r4 omsp_clock_gate_12 } \
    { execution_unit_0/register_file_0/clock_gate_r3 omsp_clock_gate_13 } \
    { execution_unit_0/register_file_0/clock_gate_r2 omsp_clock_gate_14 } \
    { execution_unit_0/register_file_0/clock_gate_r1 omsp_clock_gate_15 } \
    { multiplier_0/clock_gate_reshi omsp_clock_gate_16 } \
    { multiplier_0/clock_gate_reslo omsp_clock_gate_17 } \
    { multiplier_0/clock_gate_op2 omsp_clock_gate_18 } \
    { multiplier_0/clock_gate_op1 omsp_clock_gate_19 } \
    { watchdog_0/clock_gate_wdtcnt omsp_clock_gate_20 } \
    { watchdog_0/clock_gate_wdtctl omsp_clock_gate_21 } \
    { mem_backbone_0/clock_gate_bckup omsp_clock_gate_22 } \
    { execution_unit_0/clock_gate_mdb_in_buf omsp_clock_gate_23 } \
    { execution_unit_0/clock_gate_mdb_out_nxt omsp_clock_gate_24 } \
    { frontend_0/clock_gate_decode omsp_clock_gate_25 } \
    { frontend_0/clock_gate_inst_dext omsp_clock_gate_26 } \
    { frontend_0/clock_gate_inst_sext omsp_clock_gate_27 } \
    { frontend_0/clock_gate_pc omsp_clock_gate_28 } \
    { frontend_0/clock_gate_irq_num omsp_clock_gate_29 } \
    { clock_module_0/clock_gate_dbg_clk omsp_clock_gate_30 } \
    { clock_module_0/clock_gate_smclk omsp_clock_gate_31 } \
    { clock_module_0/clock_gate_aclk omsp_clock_gate_32 } \
    { watchdog_0/and_wdt_wkup omsp_and_gate_1 } \
    { sfr_0/and_nmi_wkup omsp_and_gate_2 } \
    { frontend_0/and_mclk_wkup omsp_and_gate_3 } \
    { frontend_0/and_mirq_wkup omsp_and_gate_4 } \
    { clock_module_0/and_lfxt_wkup omsp_and_gate_5 } \
    { clock_module_0/and_lfxt_en_wkup omsp_and_gate_6 } \
    { clock_module_0/and_lfxt_mclk_wkup omsp_and_gate_7 } \
    { clock_module_0/and_lfxt_dis5 omsp_and_gate_8 } \
    { clock_module_0/and_lfxt_dis4 omsp_and_gate_9 } \
    { clock_module_0/and_lfxt_dis3 omsp_and_gate_10 } \
    { clock_module_0/and_lfxt_dis2 omsp_and_gate_11 } \
    { clock_module_0/and_lfxt_dis1 omsp_and_gate_12 } \
    { clock_module_0/and_dco_wkup omsp_and_gate_13 } \
    { clock_module_0/and_dco_en_wkup omsp_and_gate_14 } \
    { clock_module_0/and_dco_mclk_wkup omsp_and_gate_15 } \
    { clock_module_0/and_dco_dis5 omsp_and_gate_16 } \
    { clock_module_0/and_dco_dis4 omsp_and_gate_17 } \
    { clock_module_0/and_dco_dis3 omsp_and_gate_18 } \
    { clock_module_0/and_dco_dis2 omsp_and_gate_19 } \
    { clock_module_0/and_dco_dis1 omsp_and_gate_20 } } 

guide_ungroup \
  -cells { div0/U1 } \
  -design { openMSP430 } 

guide_replace \
  -origin { ExTra_mutex } \
  -design { omsp_mem_backbone } \
  -input { 11 src23 } \
  -input { 11 src18 } \
  -input { 1 src25 } \
  -input { 1 src26 } \
  -output { 11 O1 } \
  -pre_resource { { 11 } RSOP_25_ADD_3 = SUB { { src23 ANY 11 } { U`b00100000000 } } } \
  -pre_resource { { 11 } RSOP_25_ADD_1 = SUB { { src18 ANY 11 } { U`b00100000000 } } } \
  -pre_resource { { 11 } RSOP_25_SEL_4 = SELECT { { src25 } { src26 } { RSOP_25_ADD_3.out.1 ANY 11 } { RSOP_25_ADD_1.out.1 ANY 11 } } } \
  -pre_assign { O1 = { RSOP_25_SEL_4.out.1 ANY 11 } } \
  -post_resource { { 11 } RSOP_25_ADD_6 = SUB { { RSOP_25_SEL_7.out.1 ANY 11 } { RSOP_25_SEL_8.out.1 ZERO 11 } } } \
  -post_resource { { 11 } RSOP_25_SEL_7 = SELECT { { src25 } { src26 } { src23 ANY 11 } { src18 ANY 11 } } } \
  -post_resource { { 9 } RSOP_25_SEL_8 = SELECT { { src25 } { src26 } { `b100000000 } { `b100000000 } } } \
  -post_resource { { 11 } RSOP_25_SEL_9 = SELECT { { src25 } { src26 } { RSOP_25_ADD_6.out.1 ANY 11 } { RSOP_25_ADD_6.out.1 ANY 11 } } } \
  -post_assign { O1 = { RSOP_25_SEL_9.out.1 ANY 11 } } 

guide_merge \
  -design { omsp_mem_backbone } \
  -datapath { DP_OP_12J5_124_4891 } \
  -input { 11 I1 } \
  -output { 11 O1 } \
  -pre_resource { { 11 } RSOP_25_ADD_6 = SUB { { I1 } { U`b00100000000 } } } \
  -pre_assign { O1 = { RSOP_25_ADD_6.out.1 } } 

guide_boundary_netlist \
  -file { netlists/S1/J5/dw-1 } \
  { saed90nm_typ_ht } 

guide_replace \
  -origin { Gensh } \
  -body { omsp_mem_backbone_DP_OP_12J5_124_4891_J5_0 } \
  -input { signed 11 I1 bin } \
  -output { 11 O1 bin } \
  -pre_resource { { 11 } OP0 = SUB { { I1 SIGN 11 } { U`b100000000 ZERO 11 } } } \
  -pre_assign { O1 = { OP0.out.1 SIGN 11 } } \
  -post_resource { { 11 } OP0 = SUB { { I1 SIGN 11 } { U`b100000000 ZERO 11 } } } \
  -post_assign { O1 = { OP0.out.1 SIGN 11 } } 

guide_boundary \
  -body { omsp_mem_backbone_DP_OP_12J5_124_4891_J5_0 } \
  -operand { I1 bin 11 } \
  -operand { OP0.out.1 bin 11 } \
  -column { I1 0 { I1[0] } } \
  -column { I1 1 { I1[1] } } \
  -column { I1 2 { I1[2] } } \
  -column { I1 3 { I1[3] } } \
  -column { I1 4 { I1[4] } } \
  -column { I1 5 { I1[5] } } \
  -column { I1 6 { I1[6] } } \
  -column { I1 7 { I1[7] } } \
  -column { I1 8 { I1[8] } } \
  -column { I1 9 { I1[9] } } \
  -column { I1 10 { I1[10] } } \
  -column { OP0.out.1 0 { I1[0] } } \
  -column { OP0.out.1 1 { I1[1] } } \
  -column { OP0.out.1 2 { I1[2] } } \
  -column { OP0.out.1 3 { I1[3] } } \
  -column { OP0.out.1 4 { I1[4] } } \
  -column { OP0.out.1 5 { I1[5] } } \
  -column { OP0.out.1 6 { I1[6] } } \
  -column { OP0.out.1 7 { I1[7] } } \
  -column { OP0.out.1 8 { O1[8] } } \
  -column { OP0.out.1 9 { O1[9] } } \
  -column { OP0.out.1 10 { O1[10] } } \
  -resource { OP0 { I1 } { OP0.out.1 } } 

guide_architecture_netlist \
  -file { netlists/S1/J5/dw-1 } \
  { saed90nm_typ_ht } 

guide_datapath \
  -design { omsp_mem_backbone } \
  -datapath { DP_OP_12J5_124_4891 } \
  -body { omsp_mem_backbone_DP_OP_12J5_124_4891_J5_0 } 

guide_inv_push \
  -design { openMSP430 } \
  -register { clock_module_0/lfxt_disable_reg } 

guide_inv_push \
  -design { openMSP430 } \
  -register { frontend_0/inst_src_bin_reg[3] } 

guide_inv_push \
  -design { openMSP430 } \
  -register { clock_module_0/dco_disable_reg } 

guide_environment \
  { { current_design openMSP430 } } 

guide_scan_input \
  -design { openMSP430 } \
  -disable_value { 0 } \
  -ports { scan_enable } 

guide_environment \
  { { current_design openMSP430 } } 

guide_change_names \
  -design { openMSP430 } \
  { { net e_state[3] e_state_3_ } \
    { net e_state[2] e_state_2_ } \
    { net e_state[1] e_state_1_ } \
    { net e_state[0] test_so2 } } 

guide_change_names \
  -design { omsp_clock_module } \
  { { cell bcsctl1_reg[5] bcsctl1_reg_5_ } \
    { cell divax_s_reg[1] divax_s_reg_1_ } \
    { cell bcsctl1_reg[4] bcsctl1_reg_4_ } \
    { cell divax_s_reg[0] divax_s_reg_0_ } \
    { cell aclk_div_reg[0] aclk_div_reg_0_ } \
    { cell aclk_div_reg[1] aclk_div_reg_1_ } \
    { cell aclk_div_reg[2] aclk_div_reg_2_ } \
    { cell bcsctl2_reg[7] bcsctl2_reg_7_ } \
    { cell bcsctl2_reg[5] bcsctl2_reg_5_ } \
    { cell bcsctl2_reg[4] bcsctl2_reg_4_ } \
    { cell mclk_div_reg[0] mclk_div_reg_0_ } \
    { cell mclk_div_reg[1] mclk_div_reg_1_ } \
    { cell mclk_div_reg[2] mclk_div_reg_2_ } \
    { cell bcsctl2_reg[3] bcsctl2_reg_3_ } \
    { cell bcsctl2_reg[2] bcsctl2_reg_2_ } \
    { cell divsx_s_reg[1] divsx_s_reg_1_ } \
    { cell bcsctl2_reg[1] bcsctl2_reg_1_ } \
    { cell divsx_s_reg[0] divsx_s_reg_0_ } \
    { cell smclk_div_reg[0] smclk_div_reg_0_ } \
    { cell smclk_div_reg[1] smclk_div_reg_1_ } \
    { cell smclk_div_reg[2] smclk_div_reg_2_ } \
    { cell divsx_ss_reg[0] divsx_ss_reg_0_ } \
    { cell divsx_ss_reg[1] divsx_ss_reg_1_ } \
    { cell divax_ss_reg[0] divax_ss_reg_0_ } \
    { cell divax_ss_reg[1] divax_ss_reg_1_ } \
    { cell bcsctl1_reg[0] bcsctl1_reg_0_ } \
    { cell bcsctl2_reg[0] bcsctl2_reg_0_ } \
    { net bcsctl1_rd[9] per_dout[14] } \
    { net bcsctl1_rd[13] per_dout[13] } \
    { net bcsctl1_rd[12] per_dout[12] } \
    { net bcsctl2_rd[7] per_dout[7] } \
    { net bcsctl2_rd[6] per_dout[6] } \
    { net bcsctl2_rd[5] per_dout[5] } \
    { net bcsctl2_rd[4] per_dout[4] } \
    { net bcsctl2_rd[3] per_dout[3] } \
    { net bcsctl2_rd[2] per_dout[2] } \
    { net bcsctl2_rd[1] per_dout[1] } \
    { net *Logic1* n_Logic1_ } \
    { net _10_net_ n_10_net_ } \
    { net _21_net_ n_21_net_ } \
    { net divax_ss[1] divax_ss_1_ } \
    { net aclk_div[2] test_so9 } \
    { net aclk_div[1] aclk_div_1_ } \
    { net por_noscan test_so7 } \
    { net n141 puc_pnd_set } } 

guide_change_names \
  -design { omsp_frontend } \
  { { cell e_state_reg[1] e_state_reg_1_ } \
    { cell e_state_reg[3] e_state_reg_3_ } \
    { cell e_state_reg[2] e_state_reg_2_ } \
    { cell i_state_reg[1] i_state_reg_1_ } \
    { cell i_state_reg[2] i_state_reg_2_ } \
    { cell inst_type_reg[2] inst_type_reg_2_ } \
    { cell inst_so_reg[7] inst_so_reg_7_ } \
    { cell inst_dest_bin_reg[2] inst_dest_bin_reg_2_ } \
    { cell inst_dest_bin_reg[0] inst_dest_bin_reg_0_ } \
    { cell inst_src_bin_reg[2] inst_src_bin_reg_2_ } \
    { cell inst_ad_reg[2] inst_ad_reg_2_ } \
    { cell pc_reg[15] pc_reg_15_ } \
    { cell pc_reg[14] pc_reg_14_ } \
    { cell pc_reg[12] pc_reg_12_ } \
    { cell pc_reg[10] pc_reg_10_ } \
    { cell pc_reg[8] pc_reg_8_ } \
    { cell pc_reg[6] pc_reg_6_ } \
    { cell pc_reg[4] pc_reg_4_ } \
    { cell pc_reg[2] pc_reg_2_ } \
    { cell irq_num_reg[0] irq_num_reg_0_ } \
    { cell inst_dest_bin_reg[1] inst_dest_bin_reg_1_ } \
    { cell inst_src_bin_reg[1] inst_src_bin_reg_1_ } \
    { cell inst_type_reg[1] inst_type_reg_1_ } \
    { cell irq_num_reg[3] irq_num_reg_3_ } \
    { cell irq_num_reg[1] irq_num_reg_1_ } \
    { cell irq_num_reg[2] irq_num_reg_2_ } \
    { cell e_state_reg[0] e_state_reg_0_ } \
    { cell inst_src_bin_reg[3] inst_src_bin_reg_3_ } \
    { cell inst_dext_reg[0] inst_dext_reg_0_ } \
    { cell inst_dest_bin_reg[3] inst_dest_bin_reg_3_ } \
    { cell pc_reg[0] pc_reg_0_ } \
    { cell inst_ad_reg[0] inst_ad_reg_0_ } \
    { cell inst_alu_reg[4] inst_alu_reg_4_ } \
    { cell inst_ad_reg[4] inst_ad_reg_4_ } \
    { cell inst_ad_reg[1] inst_ad_reg_1_ } \
    { cell inst_alu_reg[11] inst_alu_reg_11_ } \
    { cell inst_ad_reg[6] inst_ad_reg_6_ } \
    { cell inst_dext_reg[1] inst_dext_reg_1_ } \
    { cell inst_alu_reg[5] inst_alu_reg_5_ } \
    { cell inst_alu_reg[7] inst_alu_reg_7_ } \
    { cell inst_alu_reg[6] inst_alu_reg_6_ } \
    { cell inst_alu_reg[2] inst_alu_reg_2_ } \
    { cell inst_dext_reg[2] inst_dext_reg_2_ } \
    { cell inst_alu_reg[0] inst_alu_reg_0_ } \
    { cell inst_alu_reg[10] inst_alu_reg_10_ } \
    { cell inst_so_reg[1] inst_so_reg_1_ } \
    { cell inst_so_reg[2] inst_so_reg_2_ } \
    { cell inst_so_reg[0] inst_so_reg_0_ } \
    { cell inst_so_reg[3] inst_so_reg_3_ } \
    { cell inst_dext_reg[3] inst_dext_reg_3_ } \
    { cell inst_so_reg[4] inst_so_reg_4_ } \
    { cell inst_so_reg[5] inst_so_reg_5_ } \
    { cell inst_so_reg[6] inst_so_reg_6_ } \
    { cell inst_alu_reg[8] inst_alu_reg_8_ } \
    { cell inst_dext_reg[4] inst_dext_reg_4_ } \
    { cell inst_as_reg[7] inst_as_reg_7_ } \
    { cell inst_dext_reg[5] inst_dext_reg_5_ } \
    { cell inst_alu_reg[3] inst_alu_reg_3_ } \
    { cell inst_alu_reg[9] inst_alu_reg_9_ } \
    { cell inst_as_reg[6] inst_as_reg_6_ } \
    { cell inst_as_reg[0] inst_as_reg_0_ } \
    { cell inst_as_reg[2] inst_as_reg_2_ } \
    { cell inst_dext_reg[6] inst_dext_reg_6_ } \
    { cell inst_as_reg[3] inst_as_reg_3_ } \
    { cell inst_as_reg[4] inst_as_reg_4_ } \
    { cell inst_as_reg[1] inst_as_reg_1_ } \
    { cell inst_dext_reg[7] inst_dext_reg_7_ } \
    { cell inst_as_reg[5] inst_as_reg_5_ } \
    { cell inst_dext_reg[8] inst_dext_reg_8_ } \
    { cell inst_sext_reg[0] inst_sext_reg_0_ } \
    { cell inst_dext_reg[9] inst_dext_reg_9_ } \
    { cell inst_sz_reg[0] inst_sz_reg_0_ } \
    { cell inst_dext_reg[10] inst_dext_reg_10_ } \
    { cell inst_dext_reg[11] inst_dext_reg_11_ } \
    { cell inst_sext_reg[10] inst_sext_reg_10_ } \
    { cell inst_sext_reg[1] inst_sext_reg_1_ } \
    { cell inst_sext_reg[7] inst_sext_reg_7_ } \
    { cell inst_sext_reg[6] inst_sext_reg_6_ } \
    { cell inst_sext_reg[5] inst_sext_reg_5_ } \
    { cell inst_sext_reg[4] inst_sext_reg_4_ } \
    { cell inst_sext_reg[11] inst_sext_reg_11_ } \
    { cell inst_sext_reg[2] inst_sext_reg_2_ } \
    { cell inst_sext_reg[3] inst_sext_reg_3_ } \
    { cell inst_sext_reg[9] inst_sext_reg_9_ } \
    { cell inst_sext_reg[8] inst_sext_reg_8_ } \
    { cell inst_dext_reg[12] inst_dext_reg_12_ } \
    { cell i_state_reg[0] i_state_reg_0_ } \
    { cell inst_dext_reg[13] inst_dext_reg_13_ } \
    { cell inst_sext_reg[12] inst_sext_reg_12_ } \
    { cell inst_dext_reg[14] inst_dext_reg_14_ } \
    { cell inst_sext_reg[13] inst_sext_reg_13_ } \
    { cell inst_dext_reg[15] inst_dext_reg_15_ } \
    { cell inst_sext_reg[14] inst_sext_reg_14_ } \
    { cell inst_sext_reg[15] inst_sext_reg_15_ } \
    { cell pc_reg[1] pc_reg_1_ } \
    { cell pc_reg[3] pc_reg_3_ } \
    { cell pc_reg[5] pc_reg_5_ } \
    { cell pc_reg[7] pc_reg_7_ } \
    { cell pc_reg[9] pc_reg_9_ } \
    { cell pc_reg[11] pc_reg_11_ } \
    { cell pc_reg[13] pc_reg_13_ } \
    { cell inst_jmp_bin_reg[2] inst_jmp_bin_reg_2_ } \
    { cell inst_src_bin_reg[0] inst_src_bin_reg_0_ } \
    { cell inst_type_reg[0] inst_type_reg_0_ } \
    { cell inst_alu_reg[1] inst_alu_reg_1_ } \
    { cell inst_sz_reg[1] inst_sz_reg_1_ } \
    { net ext_nxt[0] mdb_in[0] } \
    { net pc_incr[0] pc[0] } \
    { net inst_sz_nxt[0] inst_sz_nxt_0_ } \
    { net inst_sz[0] inst_sz_0_ } \
    { net _0_net_ n_0_net_ } \
    { net _1_net_ n_1_net_ } \
    { net pmem_busy test_so1 } \
    { net ext_nxt[15] ext_nxt_15_ } \
    { net ext_nxt[14] ext_nxt_14_ } \
    { net ext_nxt[13] ext_nxt_13_ } \
    { net ext_nxt[12] ext_nxt_12_ } \
    { net ext_nxt[11] ext_nxt_11_ } \
    { net ext_nxt[10] ext_nxt_10_ } \
    { net ext_nxt[9] ext_nxt_9_ } \
    { net ext_nxt[8] ext_nxt_8_ } \
    { net ext_nxt[7] ext_nxt_7_ } \
    { net ext_nxt[6] ext_nxt_6_ } \
    { net ext_nxt[5] ext_nxt_5_ } \
    { net ext_nxt[4] ext_nxt_4_ } \
    { net ext_nxt[3] ext_nxt_3_ } \
    { net ext_nxt[2] ext_nxt_2_ } \
    { net ext_nxt[1] ext_nxt_1_ } \
    { net inst_type_nxt[2] inst_type_nxt_2_ } \
    { net inst_jmp_bin[2] inst_jmp_bin_2_ } \
    { net add_x_39/n2 add_x_39_n2 } } 

guide_change_names \
  -design { omsp_execution_unit } \
  { { cell mdb_in_buf_reg[8] mdb_in_buf_reg_8_ } \
    { cell mdb_in_buf_reg[15] mdb_in_buf_reg_15_ } \
    { cell mdb_in_buf_reg[14] mdb_in_buf_reg_14_ } \
    { cell mdb_in_buf_reg[13] mdb_in_buf_reg_13_ } \
    { cell mdb_in_buf_reg[12] mdb_in_buf_reg_12_ } \
    { cell mdb_in_buf_reg[11] mdb_in_buf_reg_11_ } \
    { cell mdb_in_buf_reg[10] mdb_in_buf_reg_10_ } \
    { cell mdb_in_buf_reg[9] mdb_in_buf_reg_9_ } \
    { cell mdb_in_buf_reg[0] mdb_in_buf_reg_0_ } \
    { cell mdb_in_buf_reg[7] mdb_in_buf_reg_7_ } \
    { cell mdb_in_buf_reg[6] mdb_in_buf_reg_6_ } \
    { cell mdb_in_buf_reg[5] mdb_in_buf_reg_5_ } \
    { cell mdb_in_buf_reg[4] mdb_in_buf_reg_4_ } \
    { cell mdb_in_buf_reg[3] mdb_in_buf_reg_3_ } \
    { cell mdb_in_buf_reg[2] mdb_in_buf_reg_2_ } \
    { cell mdb_in_buf_reg[1] mdb_in_buf_reg_1_ } \
    { cell mdb_out_nxt_reg[0] mdb_out_nxt_reg_0_ } \
    { cell mdb_out_nxt_reg[1] mdb_out_nxt_reg_1_ } \
    { cell mdb_out_nxt_reg[2] mdb_out_nxt_reg_2_ } \
    { cell mdb_out_nxt_reg[3] mdb_out_nxt_reg_3_ } \
    { cell mdb_out_nxt_reg[4] mdb_out_nxt_reg_4_ } \
    { cell mdb_out_nxt_reg[5] mdb_out_nxt_reg_5_ } \
    { cell mdb_out_nxt_reg[6] mdb_out_nxt_reg_6_ } \
    { cell mdb_out_nxt_reg[7] mdb_out_nxt_reg_7_ } \
    { cell mdb_out_nxt_reg[8] mdb_out_nxt_reg_8_ } \
    { cell mdb_out_nxt_reg[9] mdb_out_nxt_reg_9_ } \
    { cell mdb_out_nxt_reg[10] mdb_out_nxt_reg_10_ } \
    { cell mdb_out_nxt_reg[11] mdb_out_nxt_reg_11_ } \
    { cell mdb_out_nxt_reg[12] mdb_out_nxt_reg_12_ } \
    { cell mdb_out_nxt_reg[13] mdb_out_nxt_reg_13_ } \
    { cell mdb_out_nxt_reg[14] mdb_out_nxt_reg_14_ } \
    { cell mdb_out_nxt_reg[15] mdb_out_nxt_reg_15_ } \
    { net inst_ad_0 inst_ad[0] } } 

guide_change_names \
  -design { omsp_mem_backbone } \
  { { cell eu_mdb_in_sel_reg[0] eu_mdb_in_sel_reg_0_ } \
    { cell dbg_mem_din_sel_reg[1] dbg_mem_din_sel_reg_1_ } \
    { cell dbg_mem_din_sel_reg[0] dbg_mem_din_sel_reg_0_ } \
    { cell pmem_dout_bckup_reg[15] pmem_dout_bckup_reg_15_ } \
    { cell pmem_dout_bckup_reg[14] pmem_dout_bckup_reg_14_ } \
    { cell pmem_dout_bckup_reg[13] pmem_dout_bckup_reg_13_ } \
    { cell pmem_dout_bckup_reg[12] pmem_dout_bckup_reg_12_ } \
    { cell pmem_dout_bckup_reg[11] pmem_dout_bckup_reg_11_ } \
    { cell pmem_dout_bckup_reg[10] pmem_dout_bckup_reg_10_ } \
    { cell pmem_dout_bckup_reg[9] pmem_dout_bckup_reg_9_ } \
    { cell pmem_dout_bckup_reg[8] pmem_dout_bckup_reg_8_ } \
    { cell pmem_dout_bckup_reg[7] pmem_dout_bckup_reg_7_ } \
    { cell pmem_dout_bckup_reg[6] pmem_dout_bckup_reg_6_ } \
    { cell pmem_dout_bckup_reg[5] pmem_dout_bckup_reg_5_ } \
    { cell pmem_dout_bckup_reg[4] pmem_dout_bckup_reg_4_ } \
    { cell pmem_dout_bckup_reg[3] pmem_dout_bckup_reg_3_ } \
    { cell pmem_dout_bckup_reg[2] pmem_dout_bckup_reg_2_ } \
    { cell pmem_dout_bckup_reg[1] pmem_dout_bckup_reg_1_ } \
    { cell pmem_dout_bckup_reg[0] pmem_dout_bckup_reg_0_ } \
    { cell per_dout_val_reg[15] per_dout_val_reg_15_ } \
    { cell per_dout_val_reg[10] per_dout_val_reg_10_ } \
    { cell per_dout_val_reg[13] per_dout_val_reg_13_ } \
    { cell per_dout_val_reg[12] per_dout_val_reg_12_ } \
    { cell per_dout_val_reg[9] per_dout_val_reg_9_ } \
    { cell per_dout_val_reg[2] per_dout_val_reg_2_ } \
    { cell per_dout_val_reg[14] per_dout_val_reg_14_ } \
    { cell per_dout_val_reg[7] per_dout_val_reg_7_ } \
    { cell per_dout_val_reg[11] per_dout_val_reg_11_ } \
    { cell per_dout_val_reg[8] per_dout_val_reg_8_ } \
    { cell per_dout_val_reg[5] per_dout_val_reg_5_ } \
    { cell per_dout_val_reg[6] per_dout_val_reg_6_ } \
    { cell per_dout_val_reg[1] per_dout_val_reg_1_ } \
    { cell per_dout_val_reg[3] per_dout_val_reg_3_ } \
    { cell per_dout_val_reg[0] per_dout_val_reg_0_ } \
    { cell per_dout_val_reg[4] per_dout_val_reg_4_ } \
    { cell eu_mdb_in_sel_reg[1] eu_mdb_in_sel_reg_1_ } \
    { net fe_pmem_addr[10] fe_mab[10] } \
    { net fe_pmem_addr[9] fe_mab[9] } \
    { net fe_pmem_addr[8] fe_mab[8] } \
    { net fe_pmem_addr[7] fe_mab[7] } \
    { net fe_pmem_addr[6] fe_mab[6] } \
    { net fe_pmem_addr[5] fe_mab[5] } \
    { net fe_pmem_addr[4] fe_mab[4] } \
    { net fe_pmem_addr[3] fe_mab[3] } \
    { net fe_pmem_addr[2] fe_mab[2] } \
    { net fe_pmem_addr[1] fe_mab[1] } \
    { net fe_pmem_addr[0] fe_mab[0] } \
    { net eu_pmem_addr[10] eu_mab[10] } \
    { net eu_pmem_addr[9] eu_mab[9] } \
    { net eu_pmem_addr[8] eu_mab[8] } \
    { net eu_pmem_addr[7] eu_mab[7] } \
    { net eu_pmem_addr[6] eu_mab[6] } \
    { net eu_pmem_addr[5] eu_mab[5] } \
    { net eu_pmem_addr[4] eu_mab[4] } \
    { net eu_pmem_addr[3] eu_mab[3] } \
    { net eu_pmem_addr[2] eu_mab[2] } \
    { net eu_pmem_addr[1] eu_mab[1] } \
    { net eu_pmem_addr[0] eu_mab[0] } \
    { net dbg_pmem_addr[10] dbg_mem_addr[11] } \
    { net dbg_pmem_addr[9] dbg_mem_addr[10] } \
    { net dbg_pmem_addr[8] dbg_mem_addr[9] } \
    { net dbg_pmem_addr[7] dbg_mem_addr[8] } \
    { net dbg_pmem_addr[6] dbg_mem_addr[7] } \
    { net dbg_pmem_addr[5] dbg_mem_addr[6] } \
    { net dbg_pmem_addr[4] dbg_mem_addr[5] } \
    { net dbg_pmem_addr[3] dbg_mem_addr[4] } \
    { net dbg_pmem_addr[2] dbg_mem_addr[3] } \
    { net dbg_pmem_addr[1] dbg_mem_addr[2] } \
    { net dbg_pmem_addr[0] dbg_mem_addr[1] } \
    { net eu_mdb_in_sel[1] eu_mdb_in_sel_1_ } \
    { net dbg_mem_din_sel[1] dbg_mem_din_sel_1_ } } 

guide_change_names \
  -design { omsp_sfr } \
  { { net per_din_0 per_din[0] } \
    { net n135 per_addr[2] } \
    { net reg_rd[6] per_dout[12] } \
    { net reg_rd_4 per_dout[9] } \
    { net N58 per_dout[4] } \
    { net ie1[4] ie1_4_ } \
    { net ifg1[4] ifg1_4_ } \
    { net nmi_dly test_so1 } \
    { net _0_net_ n_0_net_ } } 

guide_change_names \
  -design { omsp_watchdog } \
  { { port per_dout[15] per_dout_15_ } \
    { port per_dout[14] per_dout_14_ } \
    { port per_dout[13] per_dout_13_ } \
    { port per_dout[12] per_dout_12_ } \
    { port per_dout[11]_BAR per_dout_11__BAR } \
    { port per_dout[10] per_dout_10_ } \
    { port per_dout[9] per_dout_9_ } \
    { port per_dout[8] per_dout_8_ } \
    { port per_dout[7] per_dout_7_ } \
    { port per_dout[6] per_dout_6_ } \
    { port per_dout[5] per_dout_5_ } \
    { port per_dout[4] per_dout_4_ } \
    { port per_dout[3] per_dout_3_ } \
    { port per_dout[2] per_dout_2_ } \
    { port per_dout[1] per_dout_1_ } \
    { port per_dout[0] per_dout_0_ } \
    { cell wdtctl_reg[7] wdtctl_reg_7_ } \
    { cell wdtctl_reg[6] wdtctl_reg_6_ } \
    { cell wdtctl_reg[5] wdtctl_reg_5_ } \
    { cell wdtctl_reg[4] wdtctl_reg_4_ } \
    { cell wdtctl_reg[3] wdtctl_reg_3_ } \
    { cell wdtctl_reg[2] wdtctl_reg_2_ } \
    { cell wdtctl_reg[1] wdtctl_reg_1_ } \
    { cell wdtctl_reg[0] wdtctl_reg_0_ } \
    { cell wdtisx_s_reg[0] wdtisx_s_reg_0_ } \
    { cell wdtisx_s_reg[1] wdtisx_s_reg_1_ } \
    { cell wdtcnt_reg[1] wdtcnt_reg_1_ } \
    { cell wdtcnt_reg[0] wdtcnt_reg_0_ } \
    { cell wdtcnt_reg[15] wdtcnt_reg_15_ } \
    { cell wdtcnt_reg[14] wdtcnt_reg_14_ } \
    { cell wdtcnt_reg[13] wdtcnt_reg_13_ } \
    { cell wdtcnt_reg[12] wdtcnt_reg_12_ } \
    { cell wdtcnt_reg[11] wdtcnt_reg_11_ } \
    { cell wdtcnt_reg[10] wdtcnt_reg_10_ } \
    { cell wdtcnt_reg[9] wdtcnt_reg_9_ } \
    { cell wdtcnt_reg[8] wdtcnt_reg_8_ } \
    { cell wdtcnt_reg[7] wdtcnt_reg_7_ } \
    { cell wdtcnt_reg[6] wdtcnt_reg_6_ } \
    { cell wdtcnt_reg[5] wdtcnt_reg_5_ } \
    { cell wdtcnt_reg[4] wdtcnt_reg_4_ } \
    { cell wdtcnt_reg[3] wdtcnt_reg_3_ } \
    { cell wdtcnt_reg[2] wdtcnt_reg_2_ } \
    { cell wdtisx_ss_reg[1] wdtisx_ss_reg_1_ } \
    { cell wdtisx_ss_reg[0] wdtisx_ss_reg_0_ } \
    { net per_din_4 per_din[4] } \
    { net per_din_3 per_din[3] } \
    { net per_din_2 per_din[2] } \
    { net per_din_1 per_din[1] } \
    { net per_din_0 per_din[0] } \
    { net per_dout_14 per_dout_14_ } \
    { net per_dout_7 per_dout_7_ } \
    { net per_dout_6 per_dout_6_ } \
    { net per_dout[4] per_dout_4_ } \
    { net per_dout[3] per_dout_3_ } \
    { net per_dout[2] per_dout_2_ } \
    { net per_dout[1] per_dout_1_ } \
    { net per_dout[0] per_dout_0_ } \
    { net reg_wr[0] reg_wr_0_ } \
    { net wdtcnt_clr_sync_dly test_so3 } \
    { net _0_net_ n_0_net_ } \
    { net n85 per_dout_11__BAR } } 

guide_change_names \
  -design { omsp_multiplier } \
  { { cell op1_reg[15] op1_reg_15_ } \
    { cell op1_reg[14] op1_reg_14_ } \
    { cell op1_reg[13] op1_reg_13_ } \
    { cell op1_reg[12] op1_reg_12_ } \
    { cell op1_reg[11] op1_reg_11_ } \
    { cell op1_reg[10] op1_reg_10_ } \
    { cell op1_reg[9] op1_reg_9_ } \
    { cell op1_reg[8] op1_reg_8_ } \
    { cell op1_reg[7] op1_reg_7_ } \
    { cell op1_reg[6] op1_reg_6_ } \
    { cell op1_reg[5] op1_reg_5_ } \
    { cell op1_reg[4] op1_reg_4_ } \
    { cell op1_reg[3] op1_reg_3_ } \
    { cell op1_reg[2] op1_reg_2_ } \
    { cell op1_reg[1] op1_reg_1_ } \
    { cell op1_reg[0] op1_reg_0_ } \
    { cell op2_reg[15] op2_reg_15_ } \
    { cell op2_reg[14] op2_reg_14_ } \
    { cell op2_reg[13] op2_reg_13_ } \
    { cell op2_reg[12] op2_reg_12_ } \
    { cell op2_reg[11] op2_reg_11_ } \
    { cell op2_reg[10] op2_reg_10_ } \
    { cell op2_reg[9] op2_reg_9_ } \
    { cell op2_reg[8] op2_reg_8_ } \
    { cell op2_reg[7] op2_reg_7_ } \
    { cell op2_reg[6] op2_reg_6_ } \
    { cell op2_reg[5] op2_reg_5_ } \
    { cell op2_reg[4] op2_reg_4_ } \
    { cell op2_reg[3] op2_reg_3_ } \
    { cell op2_reg[2] op2_reg_2_ } \
    { cell op2_reg[1] op2_reg_1_ } \
    { cell op2_reg[0] op2_reg_0_ } \
    { cell cycle_reg[1] cycle_reg_1_ } \
    { cell cycle_reg[0] cycle_reg_0_ } \
    { cell sumext_s_reg[1] sumext_s_reg_1_ } \
    { cell sumext_s_reg[0] sumext_s_reg_0_ } \
    { cell reshi_reg[15] reshi_reg_15_ } \
    { cell reshi_reg[14] reshi_reg_14_ } \
    { cell reshi_reg[13] reshi_reg_13_ } \
    { cell reshi_reg[12] reshi_reg_12_ } \
    { cell reshi_reg[11] reshi_reg_11_ } \
    { cell reshi_reg[10] reshi_reg_10_ } \
    { cell reshi_reg[9] reshi_reg_9_ } \
    { cell reshi_reg[8] reshi_reg_8_ } \
    { cell reshi_reg[7] reshi_reg_7_ } \
    { cell reshi_reg[6] reshi_reg_6_ } \
    { cell reshi_reg[5] reshi_reg_5_ } \
    { cell reshi_reg[4] reshi_reg_4_ } \
    { cell reshi_reg[3] reshi_reg_3_ } \
    { cell reshi_reg[2] reshi_reg_2_ } \
    { cell reshi_reg[1] reshi_reg_1_ } \
    { cell reshi_reg[0] reshi_reg_0_ } \
    { cell reslo_reg[15] reslo_reg_15_ } \
    { cell reslo_reg[14] reslo_reg_14_ } \
    { cell reslo_reg[13] reslo_reg_13_ } \
    { cell reslo_reg[12] reslo_reg_12_ } \
    { cell reslo_reg[11] reslo_reg_11_ } \
    { cell reslo_reg[10] reslo_reg_10_ } \
    { cell reslo_reg[9] reslo_reg_9_ } \
    { cell reslo_reg[8] reslo_reg_8_ } \
    { cell reslo_reg[7] reslo_reg_7_ } \
    { cell reslo_reg[6] reslo_reg_6_ } \
    { cell reslo_reg[5] reslo_reg_5_ } \
    { cell reslo_reg[4] reslo_reg_4_ } \
    { cell reslo_reg[3] reslo_reg_3_ } \
    { cell reslo_reg[2] reslo_reg_2_ } \
    { cell reslo_reg[1] reslo_reg_1_ } \
    { cell reslo_reg[0] reslo_reg_0_ } \
    { net sumext_s[1] test_so2 } \
    { net sumext_s[0] sumext_s_0_ } \
    { net n74 test_so1 } \
    { net intadd_0/B[29] intadd_0_B_29_ } \
    { net intadd_0/B[28] intadd_0_B_28_ } \
    { net intadd_0/B[27] intadd_0_B_27_ } \
    { net intadd_0/B[26] intadd_0_B_26_ } \
    { net intadd_0/B[25] intadd_0_B_25_ } \
    { net intadd_0/B[24] intadd_0_B_24_ } \
    { net intadd_0/B[23] intadd_0_B_23_ } \
    { net intadd_0/B[22] intadd_0_B_22_ } \
    { net intadd_0/B[21] intadd_0_B_21_ } \
    { net intadd_0/B[20] intadd_0_B_20_ } \
    { net intadd_0/B[19] intadd_0_B_19_ } \
    { net intadd_0/B[18] intadd_0_B_18_ } \
    { net intadd_0/B[17] intadd_0_B_17_ } \
    { net intadd_0/B[16] intadd_0_B_16_ } \
    { net intadd_0/B[15] intadd_0_B_15_ } \
    { net intadd_0/B[14] intadd_0_B_14_ } \
    { net intadd_0/B[13] intadd_0_B_13_ } \
    { net intadd_0/B[12] intadd_0_B_12_ } \
    { net intadd_0/B[11] intadd_0_B_11_ } \
    { net intadd_0/B[10] intadd_0_B_10_ } \
    { net intadd_0/B[9] intadd_0_B_9_ } \
    { net intadd_0/B[8] intadd_0_B_8_ } \
    { net intadd_0/B[7] intadd_0_B_7_ } \
    { net intadd_0/B[6] intadd_0_B_6_ } \
    { net intadd_0/B[5] intadd_0_B_5_ } \
    { net intadd_0/B[4] intadd_0_B_4_ } \
    { net intadd_0/B[3] intadd_0_B_3_ } \
    { net intadd_0/B[2] intadd_0_B_2_ } \
    { net intadd_0/B[1] intadd_0_B_1_ } \
    { net intadd_0/B[0] intadd_0_B_0_ } \
    { net intadd_0/CI intadd_0_CI } \
    { net intadd_0/SUM[29] intadd_0_SUM_29_ } \
    { net intadd_0/SUM[28] intadd_0_SUM_28_ } \
    { net intadd_0/SUM[27] intadd_0_SUM_27_ } \
    { net intadd_0/SUM[26] intadd_0_SUM_26_ } \
    { net intadd_0/SUM[25] intadd_0_SUM_25_ } \
    { net intadd_0/SUM[24] intadd_0_SUM_24_ } \
    { net intadd_0/SUM[23] intadd_0_SUM_23_ } \
    { net intadd_0/SUM[22] intadd_0_SUM_22_ } \
    { net intadd_0/SUM[21] intadd_0_SUM_21_ } \
    { net intadd_0/SUM[20] intadd_0_SUM_20_ } \
    { net intadd_0/SUM[19] intadd_0_SUM_19_ } \
    { net intadd_0/SUM[18] intadd_0_SUM_18_ } \
    { net intadd_0/SUM[17] intadd_0_SUM_17_ } \
    { net intadd_0/SUM[16] intadd_0_SUM_16_ } \
    { net intadd_0/SUM[15] intadd_0_SUM_15_ } \
    { net intadd_0/SUM[14] intadd_0_SUM_14_ } \
    { net intadd_0/SUM[13] intadd_0_SUM_13_ } \
    { net intadd_0/SUM[12] intadd_0_SUM_12_ } \
    { net intadd_0/SUM[11] intadd_0_SUM_11_ } \
    { net intadd_0/SUM[10] intadd_0_SUM_10_ } \
    { net intadd_0/SUM[9] intadd_0_SUM_9_ } \
    { net intadd_0/SUM[8] intadd_0_SUM_8_ } \
    { net intadd_0/SUM[7] intadd_0_SUM_7_ } \
    { net intadd_0/SUM[6] intadd_0_SUM_6_ } \
    { net intadd_0/SUM[5] intadd_0_SUM_5_ } \
    { net intadd_0/SUM[4] intadd_0_SUM_4_ } \
    { net intadd_0/SUM[3] intadd_0_SUM_3_ } \
    { net intadd_0/SUM[2] intadd_0_SUM_2_ } \
    { net intadd_0/SUM[1] intadd_0_SUM_1_ } \
    { net intadd_0/SUM[0] intadd_0_SUM_0_ } \
    { net intadd_0/n30 intadd_0_n30 } \
    { net intadd_0/n29 intadd_0_n29 } \
    { net intadd_0/n28 intadd_0_n28 } \
    { net intadd_0/n27 intadd_0_n27 } \
    { net intadd_0/n26 intadd_0_n26 } \
    { net intadd_0/n25 intadd_0_n25 } \
    { net intadd_0/n24 intadd_0_n24 } \
    { net intadd_0/n23 intadd_0_n23 } \
    { net intadd_0/n22 intadd_0_n22 } \
    { net intadd_0/n21 intadd_0_n21 } \
    { net intadd_0/n20 intadd_0_n20 } \
    { net intadd_0/n19 intadd_0_n19 } \
    { net intadd_0/n18 intadd_0_n18 } \
    { net intadd_0/n17 intadd_0_n17 } \
    { net intadd_0/n16 intadd_0_n16 } \
    { net intadd_0/n15 intadd_0_n15 } \
    { net intadd_0/n14 intadd_0_n14 } \
    { net intadd_0/n13 intadd_0_n13 } \
    { net intadd_0/n12 intadd_0_n12 } \
    { net intadd_0/n11 intadd_0_n11 } \
    { net intadd_0/n10 intadd_0_n10 } \
    { net intadd_0/n9 intadd_0_n9 } \
    { net intadd_0/n8 intadd_0_n8 } \
    { net intadd_0/n7 intadd_0_n7 } \
    { net intadd_0/n6 intadd_0_n6 } \
    { net intadd_0/n5 intadd_0_n5 } \
    { net intadd_0/n4 intadd_0_n4 } \
    { net intadd_0/n3 intadd_0_n3 } \
    { net intadd_0/n2 intadd_0_n2 } \
    { net intadd_0/n1 intadd_0_n1 } \
    { net intadd_1/A[15] intadd_1_A_15_ } \
    { net intadd_1/A[13] intadd_1_A_13_ } \
    { net intadd_1/A[12] intadd_1_A_12_ } \
    { net intadd_1/A[11] intadd_1_A_11_ } \
    { net intadd_1/A[10] intadd_1_A_10_ } \
    { net intadd_1/A[9] intadd_1_A_9_ } \
    { net intadd_1/A[8] intadd_1_A_8_ } \
    { net intadd_1/A[7] intadd_1_A_7_ } \
    { net intadd_1/A[6] intadd_1_A_6_ } \
    { net intadd_1/A[5] intadd_1_A_5_ } \
    { net intadd_1/A[4] intadd_1_A_4_ } \
    { net intadd_1/A[3] intadd_1_A_3_ } \
    { net intadd_1/A[2] intadd_1_A_2_ } \
    { net intadd_1/A[1] intadd_1_A_1_ } \
    { net intadd_1/A[0] intadd_1_A_0_ } \
    { net intadd_1/B[15] intadd_1_B_15_ } \
    { net intadd_1/B[14] intadd_1_B_14_ } \
    { net intadd_1/B[13] intadd_1_B_13_ } \
    { net intadd_1/B[12] intadd_1_B_12_ } \
    { net intadd_1/B[11] intadd_1_B_11_ } \
    { net intadd_1/B[10] intadd_1_B_10_ } \
    { net intadd_1/B[9] intadd_1_B_9_ } \
    { net intadd_1/B[8] intadd_1_B_8_ } \
    { net intadd_1/B[7] intadd_1_B_7_ } \
    { net intadd_1/B[6] intadd_1_B_6_ } \
    { net intadd_1/B[5] intadd_1_B_5_ } \
    { net intadd_1/B[4] intadd_1_B_4_ } \
    { net intadd_1/B[3] intadd_1_B_3_ } \
    { net intadd_1/B[2] intadd_1_B_2_ } \
    { net intadd_1/B[1] intadd_1_B_1_ } \
    { net intadd_1/B[0] intadd_1_B_0_ } \
    { net intadd_1/CI intadd_1_CI } \
    { net intadd_1/SUM[15] intadd_1_SUM_15_ } \
    { net intadd_1/SUM[14] intadd_1_SUM_14_ } \
    { net intadd_1/SUM[13] intadd_1_SUM_13_ } \
    { net intadd_1/SUM[12] intadd_1_SUM_12_ } \
    { net intadd_1/SUM[11] intadd_1_SUM_11_ } \
    { net intadd_1/SUM[10] intadd_1_SUM_10_ } \
    { net intadd_1/SUM[9] intadd_1_SUM_9_ } \
    { net intadd_1/SUM[8] intadd_1_SUM_8_ } \
    { net intadd_1/SUM[7] intadd_1_SUM_7_ } \
    { net intadd_1/SUM[6] intadd_1_SUM_6_ } \
    { net intadd_1/SUM[5] intadd_1_SUM_5_ } \
    { net intadd_1/SUM[4] intadd_1_SUM_4_ } \
    { net intadd_1/SUM[3] intadd_1_SUM_3_ } \
    { net intadd_1/SUM[2] intadd_1_SUM_2_ } \
    { net intadd_1/SUM[1] intadd_1_SUM_1_ } \
    { net intadd_1/SUM[0] intadd_1_SUM_0_ } \
    { net intadd_1/n16 intadd_1_n16 } \
    { net intadd_1/n15 intadd_1_n15 } \
    { net intadd_1/n14 intadd_1_n14 } \
    { net intadd_1/n13 intadd_1_n13 } \
    { net intadd_1/n12 intadd_1_n12 } \
    { net intadd_1/n11 intadd_1_n11 } \
    { net intadd_1/n10 intadd_1_n10 } \
    { net intadd_1/n9 intadd_1_n9 } \
    { net intadd_1/n8 intadd_1_n8 } \
    { net intadd_1/n7 intadd_1_n7 } \
    { net intadd_1/n6 intadd_1_n6 } \
    { net intadd_1/n5 intadd_1_n5 } \
    { net intadd_1/n4 intadd_1_n4 } \
    { net intadd_1/n3 intadd_1_n3 } \
    { net intadd_1/n2 intadd_1_n2 } \
    { net intadd_1/n1 intadd_1_n1 } \
    { net intadd_2/CI intadd_2_CI } \
    { net intadd_2/SUM[12] intadd_2_SUM_12_ } \
    { net intadd_2/SUM[11] intadd_2_SUM_11_ } \
    { net intadd_2/SUM[10] intadd_2_SUM_10_ } \
    { net intadd_2/SUM[9] intadd_2_SUM_9_ } \
    { net intadd_2/SUM[8] intadd_2_SUM_8_ } \
    { net intadd_2/SUM[7] intadd_2_SUM_7_ } \
    { net intadd_2/SUM[6] intadd_2_SUM_6_ } \
    { net intadd_2/SUM[5] intadd_2_SUM_5_ } \
    { net intadd_2/SUM[4] intadd_2_SUM_4_ } \
    { net intadd_2/SUM[3] intadd_2_SUM_3_ } \
    { net intadd_2/SUM[2] intadd_2_SUM_2_ } \
    { net intadd_2/SUM[1] intadd_2_SUM_1_ } \
    { net intadd_2/SUM[0] intadd_2_SUM_0_ } \
    { net intadd_2/n13 intadd_2_n13 } \
    { net intadd_2/n12 intadd_2_n12 } \
    { net intadd_2/n11 intadd_2_n11 } \
    { net intadd_2/n10 intadd_2_n10 } \
    { net intadd_2/n9 intadd_2_n9 } \
    { net intadd_2/n8 intadd_2_n8 } \
    { net intadd_2/n7 intadd_2_n7 } \
    { net intadd_2/n6 intadd_2_n6 } \
    { net intadd_2/n5 intadd_2_n5 } \
    { net intadd_2/n4 intadd_2_n4 } \
    { net intadd_2/n3 intadd_2_n3 } \
    { net intadd_2/n2 intadd_2_n2 } \
    { net intadd_2/n1 intadd_2_n1 } \
    { net intadd_3/A[10] intadd_3_A_10_ } \
    { net intadd_3/A[9] intadd_3_A_9_ } \
    { net intadd_3/A[8] intadd_3_A_8_ } \
    { net intadd_3/A[7] intadd_3_A_7_ } \
    { net intadd_3/A[6] intadd_3_A_6_ } \
    { net intadd_3/A[5] intadd_3_A_5_ } \
    { net intadd_3/A[4] intadd_3_A_4_ } \
    { net intadd_3/A[3] intadd_3_A_3_ } \
    { net intadd_3/A[2] intadd_3_A_2_ } \
    { net intadd_3/A[1] intadd_3_A_1_ } \
    { net intadd_3/A[0] intadd_3_A_0_ } \
    { net intadd_3/B[10] intadd_3_B_10_ } \
    { net intadd_3/B[9] intadd_3_B_9_ } \
    { net intadd_3/B[8] intadd_3_B_8_ } \
    { net intadd_3/B[7] intadd_3_B_7_ } \
    { net intadd_3/B[6] intadd_3_B_6_ } \
    { net intadd_3/B[5] intadd_3_B_5_ } \
    { net intadd_3/B[4] intadd_3_B_4_ } \
    { net intadd_3/B[3] intadd_3_B_3_ } \
    { net intadd_3/B[2] intadd_3_B_2_ } \
    { net intadd_3/B[1] intadd_3_B_1_ } \
    { net intadd_3/B[0] intadd_3_B_0_ } \
    { net intadd_3/CI intadd_3_CI } \
    { net intadd_3/n11 intadd_3_n11 } \
    { net intadd_3/n10 intadd_3_n10 } \
    { net intadd_3/n9 intadd_3_n9 } \
    { net intadd_3/n8 intadd_3_n8 } \
    { net intadd_3/n7 intadd_3_n7 } \
    { net intadd_3/n6 intadd_3_n6 } \
    { net intadd_3/n5 intadd_3_n5 } \
    { net intadd_3/n4 intadd_3_n4 } \
    { net intadd_3/n3 intadd_3_n3 } \
    { net intadd_3/n2 intadd_3_n2 } \
    { net intadd_3/n1 intadd_3_n1 } \
    { net intadd_4/A[3] intadd_4_A_3_ } \
    { net intadd_4/A[2] intadd_4_A_2_ } \
    { net intadd_4/A[1] intadd_4_A_1_ } \
    { net intadd_4/A[0] intadd_4_A_0_ } \
    { net intadd_4/B[3] intadd_4_B_3_ } \
    { net intadd_4/B[2] intadd_4_B_2_ } \
    { net intadd_4/B[1] intadd_4_B_1_ } \
    { net intadd_4/B[0] intadd_4_B_0_ } \
    { net intadd_4/CI intadd_4_CI } \
    { net intadd_4/SUM[3] intadd_4_SUM_3_ } \
    { net intadd_4/SUM[2] intadd_4_SUM_2_ } \
    { net intadd_4/SUM[1] intadd_4_SUM_1_ } \
    { net intadd_4/SUM[0] intadd_4_SUM_0_ } \
    { net intadd_4/n4 intadd_4_n4 } \
    { net intadd_4/n3 intadd_4_n3 } \
    { net intadd_4/n2 intadd_4_n2 } \
    { net intadd_4/n1 intadd_4_n1 } } 

guide_change_names \
  -design { omsp_divider_16b } \
  { { cell op1_dividend_reg[15] op1_dividend_reg_15_ } \
    { cell op1_dividend_reg[14] op1_dividend_reg_14_ } \
    { cell op1_dividend_reg[13] op1_dividend_reg_13_ } \
    { cell op1_dividend_reg[12] op1_dividend_reg_12_ } \
    { cell op1_dividend_reg[11] op1_dividend_reg_11_ } \
    { cell op1_dividend_reg[10] op1_dividend_reg_10_ } \
    { cell op1_dividend_reg[9] op1_dividend_reg_9_ } \
    { cell op1_dividend_reg[8] op1_dividend_reg_8_ } \
    { cell op1_dividend_reg[7] op1_dividend_reg_7_ } \
    { cell op1_dividend_reg[6] op1_dividend_reg_6_ } \
    { cell op1_dividend_reg[5] op1_dividend_reg_5_ } \
    { cell op1_dividend_reg[4] op1_dividend_reg_4_ } \
    { cell op1_dividend_reg[3] op1_dividend_reg_3_ } \
    { cell op1_dividend_reg[2] op1_dividend_reg_2_ } \
    { cell op1_dividend_reg[1] op1_dividend_reg_1_ } \
    { cell op2_divisor_reg[15] op2_divisor_reg_15_ } \
    { cell op2_divisor_reg[0] op2_divisor_reg_0_ } \
    { cell op2_divisor_reg[14] op2_divisor_reg_14_ } \
    { cell op2_divisor_reg[13] op2_divisor_reg_13_ } \
    { cell op2_divisor_reg[12] op2_divisor_reg_12_ } \
    { cell op2_divisor_reg[11] op2_divisor_reg_11_ } \
    { cell op2_divisor_reg[10] op2_divisor_reg_10_ } \
    { cell op2_divisor_reg[9] op2_divisor_reg_9_ } \
    { cell op2_divisor_reg[8] op2_divisor_reg_8_ } \
    { cell op2_divisor_reg[7] op2_divisor_reg_7_ } \
    { cell op2_divisor_reg[6] op2_divisor_reg_6_ } \
    { cell op2_divisor_reg[5] op2_divisor_reg_5_ } \
    { cell op2_divisor_reg[4] op2_divisor_reg_4_ } \
    { cell op2_divisor_reg[3] op2_divisor_reg_3_ } \
    { cell op2_divisor_reg[2] op2_divisor_reg_2_ } \
    { cell op2_divisor_reg[1] op2_divisor_reg_1_ } \
    { cell remainder_reg[13] remainder_reg_13_ } \
    { cell remainder_reg[11] remainder_reg_11_ } \
    { cell remainder_reg[9] remainder_reg_9_ } \
    { cell remainder_reg[7] remainder_reg_7_ } \
    { cell remainder_reg[5] remainder_reg_5_ } \
    { cell remainder_reg[3] remainder_reg_3_ } \
    { cell remainder_reg[1] remainder_reg_1_ } \
    { cell remainder_reg[15] remainder_reg_15_ } \
    { cell remainder_reg[14] remainder_reg_14_ } \
    { cell remainder_reg[12] remainder_reg_12_ } \
    { cell remainder_reg[10] remainder_reg_10_ } \
    { cell remainder_reg[8] remainder_reg_8_ } \
    { cell remainder_reg[6] remainder_reg_6_ } \
    { cell remainder_reg[4] remainder_reg_4_ } \
    { cell remainder_reg[2] remainder_reg_2_ } \
    { cell remainder_reg[0] remainder_reg_0_ } \
    { cell quotient_reg[15] quotient_reg_15_ } \
    { cell quotient_reg[14] quotient_reg_14_ } \
    { cell quotient_reg[13] quotient_reg_13_ } \
    { cell quotient_reg[11] quotient_reg_11_ } \
    { cell quotient_reg[9] quotient_reg_9_ } \
    { cell quotient_reg[7] quotient_reg_7_ } \
    { cell quotient_reg[5] quotient_reg_5_ } \
    { cell quotient_reg[3] quotient_reg_3_ } \
    { cell op1_dividend_reg[0] op1_dividend_reg_0_ } \
    { cell quotient_reg[12] quotient_reg_12_ } \
    { cell quotient_reg[10] quotient_reg_10_ } \
    { cell quotient_reg[8] quotient_reg_8_ } \
    { cell quotient_reg[6] quotient_reg_6_ } \
    { cell quotient_reg[4] quotient_reg_4_ } \
    { cell quotient_reg[2] quotient_reg_2_ } \
    { cell quotient_reg[1] quotient_reg_1_ } \
    { cell quotient_reg[0] quotient_reg_0_ } \
    { net N35 per_dout[15] } \
    { net N38 per_dout[14] } \
    { net N41 per_dout[13] } \
    { net N44 per_dout[12] } \
    { net N47 per_dout[11] } \
    { net N50 per_dout[10] } \
    { net N53 per_dout[9] } \
    { net N56 per_dout[8] } \
    { net N59 per_dout[7] } \
    { net N62 per_dout[6] } \
    { net N65 per_dout[5] } \
    { net N68 per_dout[4] } \
    { net N71 per_dout[3] } \
    { net N74 per_dout[2] } \
    { net N77 per_dout[1] } \
    { net remainder[15] test_so2 } \
    { net remainder[14] remainder_14_ } \
    { net remainder[13] remainder_13_ } \
    { net remainder[12] test_so1 } \
    { net remainder[11] remainder_11_ } \
    { net remainder[10] remainder_10_ } \
    { net remainder[9] remainder_9_ } \
    { net remainder[8] remainder_8_ } \
    { net remainder[7] remainder_7_ } \
    { net remainder[6] remainder_6_ } \
    { net remainder[5] remainder_5_ } \
    { net remainder[4] remainder_4_ } \
    { net remainder[3] remainder_3_ } \
    { net remainder[2] remainder_2_ } \
    { net remainder[1] remainder_1_ } \
    { net remainder[0] remainder_0_ } } 

guide_change_names \
  -design { omsp_dbg } \
  { { cell mem_cnt_reg[15] mem_cnt_reg_15_ } \
    { cell mem_cnt_reg[14] mem_cnt_reg_14_ } \
    { cell mem_cnt_reg[13] mem_cnt_reg_13_ } \
    { cell mem_cnt_reg[12] mem_cnt_reg_12_ } \
    { cell mem_cnt_reg[11] mem_cnt_reg_11_ } \
    { cell mem_cnt_reg[10] mem_cnt_reg_10_ } \
    { cell mem_cnt_reg[9] mem_cnt_reg_9_ } \
    { cell mem_cnt_reg[8] mem_cnt_reg_8_ } \
    { cell mem_cnt_reg[7] mem_cnt_reg_7_ } \
    { cell mem_cnt_reg[6] mem_cnt_reg_6_ } \
    { cell mem_cnt_reg[5] mem_cnt_reg_5_ } \
    { cell mem_cnt_reg[4] mem_cnt_reg_4_ } \
    { cell mem_cnt_reg[3] mem_cnt_reg_3_ } \
    { cell mem_cnt_reg[2] mem_cnt_reg_2_ } \
    { cell mem_cnt_reg[1] mem_cnt_reg_1_ } \
    { cell mem_cnt_reg[0] mem_cnt_reg_0_ } \
    { cell mem_ctl_reg[3] mem_ctl_reg_3_ } \
    { cell mem_ctl_reg[2] mem_ctl_reg_2_ } \
    { cell mem_ctl_reg[1] mem_ctl_reg_1_ } \
    { cell mem_state_reg[1] mem_state_reg_1_ } \
    { cell mem_state_reg[0] mem_state_reg_0_ } \
    { cell cpu_ctl_reg[6] cpu_ctl_reg_6_ } \
    { cell cpu_ctl_reg[5] cpu_ctl_reg_5_ } \
    { cell cpu_ctl_reg[4] cpu_ctl_reg_4_ } \
    { cell cpu_ctl_reg[3] cpu_ctl_reg_3_ } \
    { cell inc_step_reg[0] inc_step_reg_0_ } \
    { cell inc_step_reg[1] inc_step_reg_1_ } \
    { cell cpu_stat_reg[2] cpu_stat_reg_2_ } \
    { cell mem_addr_reg[15] mem_addr_reg_15_ } \
    { cell mem_addr_reg[14] mem_addr_reg_14_ } \
    { cell mem_addr_reg[13] mem_addr_reg_13_ } \
    { cell mem_addr_reg[12] mem_addr_reg_12_ } \
    { cell mem_addr_reg[11] mem_addr_reg_11_ } \
    { cell mem_addr_reg[10] mem_addr_reg_10_ } \
    { cell mem_addr_reg[9] mem_addr_reg_9_ } \
    { cell mem_addr_reg[8] mem_addr_reg_8_ } \
    { cell mem_addr_reg[7] mem_addr_reg_7_ } \
    { cell mem_addr_reg[6] mem_addr_reg_6_ } \
    { cell mem_addr_reg[5] mem_addr_reg_5_ } \
    { cell mem_addr_reg[4] mem_addr_reg_4_ } \
    { cell mem_addr_reg[3] mem_addr_reg_3_ } \
    { cell mem_addr_reg[2] mem_addr_reg_2_ } \
    { cell mem_addr_reg[1] mem_addr_reg_1_ } \
    { cell mem_addr_reg[0] mem_addr_reg_0_ } \
    { cell mem_data_reg[4] mem_data_reg_4_ } \
    { cell mem_data_reg[6] mem_data_reg_6_ } \
    { cell mem_data_reg[15] mem_data_reg_15_ } \
    { cell mem_data_reg[14] mem_data_reg_14_ } \
    { cell mem_data_reg[13] mem_data_reg_13_ } \
    { cell mem_data_reg[12] mem_data_reg_12_ } \
    { cell mem_data_reg[11] mem_data_reg_11_ } \
    { cell mem_data_reg[10] mem_data_reg_10_ } \
    { cell mem_data_reg[9] mem_data_reg_9_ } \
    { cell mem_data_reg[8] mem_data_reg_8_ } \
    { cell mem_data_reg[7] mem_data_reg_7_ } \
    { cell mem_data_reg[5] mem_data_reg_5_ } \
    { cell mem_data_reg[3] mem_data_reg_3_ } \
    { cell mem_data_reg[2] mem_data_reg_2_ } \
    { cell mem_data_reg[1] mem_data_reg_1_ } \
    { cell mem_data_reg[0] mem_data_reg_0_ } \
    { cell cpu_stat_reg[3] cpu_stat_reg_3_ } \
    { net mem_state[1] test_so2 } } 

guide_change_names \
  -design { omsp_sync_cell_0 } \
  { { cell data_sync_reg[0] data_sync_reg_0_ } \
    { cell data_sync_reg[1] data_sync_reg_1_ } } 

guide_change_names \
  -design { omsp_sync_cell_16 } \
  { { cell data_sync_reg[0] data_sync_reg_0_ } \
    { cell data_sync_reg[1] data_sync_reg_1_ } } 

guide_change_names \
  -design { omsp_sync_cell_15 } \
  { { cell data_sync_reg[0] data_sync_reg_0_ } \
    { cell data_sync_reg[1] data_sync_reg_1_ } } 

guide_change_names \
  -design { omsp_sync_cell_14 } \
  { { cell data_sync_reg[0] data_sync_reg_0_ } \
    { cell data_sync_reg[1] data_sync_reg_1_ } } 

guide_change_names \
  -design { omsp_sync_cell_13 } \
  { { cell data_sync_reg[0] data_sync_reg_0_ } \
    { cell data_sync_reg[1] data_sync_reg_1_ } } 

guide_change_names \
  -design { omsp_sync_cell_12 } \
  { { cell data_sync_reg[0] data_sync_reg_0_ } \
    { cell data_sync_reg[1] data_sync_reg_1_ } } 

guide_change_names \
  -design { omsp_clock_mux_0 } \
  { { net in1_select_ss test_so4 } \
    { net in1_select_s test_so2 } } 

guide_change_names \
  -design { omsp_sync_cell_11 } \
  { { cell data_sync_reg[0] data_sync_reg_0_ } \
    { cell data_sync_reg[1] data_sync_reg_1_ } } 

guide_change_names \
  -design { omsp_sync_cell_10 } \
  { { cell data_sync_reg[0] data_sync_reg_0_ } \
    { cell data_sync_reg[1] data_sync_reg_1_ } } 

guide_change_names \
  -design { omsp_sync_cell_9 } \
  { { cell data_sync_reg[0] data_sync_reg_0_ } \
    { cell data_sync_reg[1] data_sync_reg_1_ } } 

guide_change_names \
  -design { omsp_clock_mux_2 } \
  { { net in1_select_ss test_so4 } \
    { net in1_select_s test_so2 } } 

guide_change_names \
  -design { omsp_sync_cell_8 } \
  { { cell data_sync_reg[0] data_sync_reg_0_ } \
    { cell data_sync_reg[1] data_sync_reg_1_ } } 

guide_change_names \
  -design { omsp_sync_cell_7 } \
  { { cell data_sync_reg[0] data_sync_reg_0_ } \
    { cell data_sync_reg[1] data_sync_reg_1_ } } 

guide_change_names \
  -design { omsp_sync_reset_0 } \
  { { cell data_sync_reg[0] data_sync_reg_0_ } \
    { cell data_sync_reg[1] data_sync_reg_1_ } \
    { net *Logic0* n_Logic0_ } \
    { net data_sync[0] data_sync_0_ } } 

guide_change_names \
  -design { omsp_sync_cell_6 } \
  { { cell data_sync_reg[0] data_sync_reg_0_ } \
    { cell data_sync_reg[1] data_sync_reg_1_ } } 

guide_change_names \
  -design { omsp_register_file } \
  { { cell r1_reg[0] r1_reg_0_ } \
    { cell r2_reg[9] r2_reg_9_ } \
    { cell r3_reg[0] r3_reg_0_ } \
    { cell r14_reg[0] r14_reg_0_ } \
    { cell r11_reg[0] r11_reg_0_ } \
    { cell r8_reg[0] r8_reg_0_ } \
    { cell r5_reg[0] r5_reg_0_ } \
    { cell r13_reg[0] r13_reg_0_ } \
    { cell r10_reg[0] r10_reg_0_ } \
    { cell r7_reg[0] r7_reg_0_ } \
    { cell r4_reg[0] r4_reg_0_ } \
    { cell r15_reg[0] r15_reg_0_ } \
    { cell r12_reg[0] r12_reg_0_ } \
    { cell r9_reg[0] r9_reg_0_ } \
    { cell r6_reg[0] r6_reg_0_ } \
    { cell r3_reg[1] r3_reg_1_ } \
    { cell r3_reg[2] r3_reg_2_ } \
    { cell r1_reg[1] r1_reg_1_ } \
    { cell r14_reg[1] r14_reg_1_ } \
    { cell r12_reg[1] r12_reg_1_ } \
    { cell r4_reg[1] r4_reg_1_ } \
    { cell r10_reg[1] r10_reg_1_ } \
    { cell r9_reg[1] r9_reg_1_ } \
    { cell r8_reg[1] r8_reg_1_ } \
    { cell r7_reg[1] r7_reg_1_ } \
    { cell r6_reg[1] r6_reg_1_ } \
    { cell r15_reg[1] r15_reg_1_ } \
    { cell r13_reg[1] r13_reg_1_ } \
    { cell r11_reg[1] r11_reg_1_ } \
    { cell r5_reg[1] r5_reg_1_ } \
    { cell r1_reg[2] r1_reg_2_ } \
    { cell r15_reg[2] r15_reg_2_ } \
    { cell r13_reg[2] r13_reg_2_ } \
    { cell r11_reg[2] r11_reg_2_ } \
    { cell r9_reg[2] r9_reg_2_ } \
    { cell r8_reg[2] r8_reg_2_ } \
    { cell r7_reg[2] r7_reg_2_ } \
    { cell r6_reg[2] r6_reg_2_ } \
    { cell r5_reg[2] r5_reg_2_ } \
    { cell r14_reg[2] r14_reg_2_ } \
    { cell r12_reg[2] r12_reg_2_ } \
    { cell r10_reg[2] r10_reg_2_ } \
    { cell r4_reg[2] r4_reg_2_ } \
    { cell r3_reg[3] r3_reg_3_ } \
    { cell r2_reg[3] r2_reg_3_ } \
    { cell r1_reg[3] r1_reg_3_ } \
    { cell r15_reg[3] r15_reg_3_ } \
    { cell r13_reg[3] r13_reg_3_ } \
    { cell r11_reg[3] r11_reg_3_ } \
    { cell r9_reg[3] r9_reg_3_ } \
    { cell r8_reg[3] r8_reg_3_ } \
    { cell r7_reg[3] r7_reg_3_ } \
    { cell r6_reg[3] r6_reg_3_ } \
    { cell r5_reg[3] r5_reg_3_ } \
    { cell r14_reg[3] r14_reg_3_ } \
    { cell r12_reg[3] r12_reg_3_ } \
    { cell r10_reg[3] r10_reg_3_ } \
    { cell r4_reg[3] r4_reg_3_ } \
    { cell r3_reg[4] r3_reg_4_ } \
    { cell r2_reg[4] r2_reg_4_ } \
    { cell r1_reg[4] r1_reg_4_ } \
    { cell r15_reg[4] r15_reg_4_ } \
    { cell r14_reg[4] r14_reg_4_ } \
    { cell r13_reg[4] r13_reg_4_ } \
    { cell r12_reg[4] r12_reg_4_ } \
    { cell r11_reg[4] r11_reg_4_ } \
    { cell r10_reg[4] r10_reg_4_ } \
    { cell r9_reg[4] r9_reg_4_ } \
    { cell r8_reg[4] r8_reg_4_ } \
    { cell r7_reg[4] r7_reg_4_ } \
    { cell r6_reg[4] r6_reg_4_ } \
    { cell r5_reg[4] r5_reg_4_ } \
    { cell r4_reg[4] r4_reg_4_ } \
    { cell r3_reg[7] r3_reg_7_ } \
    { cell r3_reg[5] r3_reg_5_ } \
    { cell r2_reg[5] r2_reg_5_ } \
    { cell r2_reg[7] r2_reg_7_ } \
    { cell r1_reg[5] r1_reg_5_ } \
    { cell r1_reg[7] r1_reg_7_ } \
    { cell r15_reg[5] r15_reg_5_ } \
    { cell r13_reg[5] r13_reg_5_ } \
    { cell r11_reg[5] r11_reg_5_ } \
    { cell r9_reg[5] r9_reg_5_ } \
    { cell r8_reg[5] r8_reg_5_ } \
    { cell r7_reg[5] r7_reg_5_ } \
    { cell r6_reg[5] r6_reg_5_ } \
    { cell r5_reg[5] r5_reg_5_ } \
    { cell r14_reg[5] r14_reg_5_ } \
    { cell r12_reg[5] r12_reg_5_ } \
    { cell r10_reg[5] r10_reg_5_ } \
    { cell r4_reg[5] r4_reg_5_ } \
    { cell r14_reg[7] r14_reg_7_ } \
    { cell r12_reg[7] r12_reg_7_ } \
    { cell r10_reg[7] r10_reg_7_ } \
    { cell r8_reg[7] r8_reg_7_ } \
    { cell r6_reg[7] r6_reg_7_ } \
    { cell r4_reg[7] r4_reg_7_ } \
    { cell r15_reg[7] r15_reg_7_ } \
    { cell r13_reg[7] r13_reg_7_ } \
    { cell r11_reg[7] r11_reg_7_ } \
    { cell r9_reg[7] r9_reg_7_ } \
    { cell r7_reg[7] r7_reg_7_ } \
    { cell r5_reg[7] r5_reg_7_ } \
    { cell r3_reg[6] r3_reg_6_ } \
    { cell r2_reg[6] r2_reg_6_ } \
    { cell r1_reg[6] r1_reg_6_ } \
    { cell r9_reg[6] r9_reg_6_ } \
    { cell r8_reg[6] r8_reg_6_ } \
    { cell r7_reg[6] r7_reg_6_ } \
    { cell r6_reg[6] r6_reg_6_ } \
    { cell r5_reg[6] r5_reg_6_ } \
    { cell r15_reg[6] r15_reg_6_ } \
    { cell r13_reg[6] r13_reg_6_ } \
    { cell r11_reg[6] r11_reg_6_ } \
    { cell r14_reg[6] r14_reg_6_ } \
    { cell r12_reg[6] r12_reg_6_ } \
    { cell r10_reg[6] r10_reg_6_ } \
    { cell r4_reg[6] r4_reg_6_ } \
    { cell r3_reg[8] r3_reg_8_ } \
    { cell r1_reg[8] r1_reg_8_ } \
    { cell r15_reg[8] r15_reg_8_ } \
    { cell r14_reg[8] r14_reg_8_ } \
    { cell r13_reg[8] r13_reg_8_ } \
    { cell r12_reg[8] r12_reg_8_ } \
    { cell r11_reg[8] r11_reg_8_ } \
    { cell r10_reg[8] r10_reg_8_ } \
    { cell r9_reg[8] r9_reg_8_ } \
    { cell r8_reg[8] r8_reg_8_ } \
    { cell r7_reg[8] r7_reg_8_ } \
    { cell r6_reg[8] r6_reg_8_ } \
    { cell r5_reg[8] r5_reg_8_ } \
    { cell r4_reg[8] r4_reg_8_ } \
    { cell r3_reg[11] r3_reg_11_ } \
    { cell r1_reg[11] r1_reg_11_ } \
    { cell r3_reg[10] r3_reg_10_ } \
    { cell r15_reg[11] r15_reg_11_ } \
    { cell r14_reg[11] r14_reg_11_ } \
    { cell r13_reg[11] r13_reg_11_ } \
    { cell r12_reg[11] r12_reg_11_ } \
    { cell r11_reg[11] r11_reg_11_ } \
    { cell r10_reg[11] r10_reg_11_ } \
    { cell r9_reg[11] r9_reg_11_ } \
    { cell r8_reg[11] r8_reg_11_ } \
    { cell r7_reg[11] r7_reg_11_ } \
    { cell r6_reg[11] r6_reg_11_ } \
    { cell r5_reg[11] r5_reg_11_ } \
    { cell r4_reg[11] r4_reg_11_ } \
    { cell r3_reg[9] r3_reg_9_ } \
    { cell r1_reg[10] r1_reg_10_ } \
    { cell r3_reg[12] r3_reg_12_ } \
    { cell r1_reg[9] r1_reg_9_ } \
    { cell r15_reg[10] r15_reg_10_ } \
    { cell r14_reg[10] r14_reg_10_ } \
    { cell r13_reg[10] r13_reg_10_ } \
    { cell r12_reg[10] r12_reg_10_ } \
    { cell r11_reg[10] r11_reg_10_ } \
    { cell r10_reg[10] r10_reg_10_ } \
    { cell r9_reg[10] r9_reg_10_ } \
    { cell r8_reg[10] r8_reg_10_ } \
    { cell r7_reg[10] r7_reg_10_ } \
    { cell r6_reg[10] r6_reg_10_ } \
    { cell r5_reg[10] r5_reg_10_ } \
    { cell r4_reg[10] r4_reg_10_ } \
    { cell r15_reg[9] r15_reg_9_ } \
    { cell r14_reg[9] r14_reg_9_ } \
    { cell r13_reg[9] r13_reg_9_ } \
    { cell r12_reg[9] r12_reg_9_ } \
    { cell r11_reg[9] r11_reg_9_ } \
    { cell r10_reg[9] r10_reg_9_ } \
    { cell r9_reg[9] r9_reg_9_ } \
    { cell r8_reg[9] r8_reg_9_ } \
    { cell r7_reg[9] r7_reg_9_ } \
    { cell r6_reg[9] r6_reg_9_ } \
    { cell r5_reg[9] r5_reg_9_ } \
    { cell r4_reg[9] r4_reg_9_ } \
    { cell r1_reg[12] r1_reg_12_ } \
    { cell r15_reg[12] r15_reg_12_ } \
    { cell r14_reg[12] r14_reg_12_ } \
    { cell r13_reg[12] r13_reg_12_ } \
    { cell r12_reg[12] r12_reg_12_ } \
    { cell r11_reg[12] r11_reg_12_ } \
    { cell r10_reg[12] r10_reg_12_ } \
    { cell r9_reg[12] r9_reg_12_ } \
    { cell r8_reg[12] r8_reg_12_ } \
    { cell r7_reg[12] r7_reg_12_ } \
    { cell r6_reg[12] r6_reg_12_ } \
    { cell r5_reg[12] r5_reg_12_ } \
    { cell r4_reg[12] r4_reg_12_ } \
    { cell r3_reg[13] r3_reg_13_ } \
    { cell r3_reg[14] r3_reg_14_ } \
    { cell r1_reg[13] r1_reg_13_ } \
    { cell r15_reg[13] r15_reg_13_ } \
    { cell r14_reg[13] r14_reg_13_ } \
    { cell r13_reg[13] r13_reg_13_ } \
    { cell r12_reg[13] r12_reg_13_ } \
    { cell r11_reg[13] r11_reg_13_ } \
    { cell r10_reg[13] r10_reg_13_ } \
    { cell r9_reg[13] r9_reg_13_ } \
    { cell r8_reg[13] r8_reg_13_ } \
    { cell r7_reg[13] r7_reg_13_ } \
    { cell r6_reg[13] r6_reg_13_ } \
    { cell r5_reg[13] r5_reg_13_ } \
    { cell r4_reg[13] r4_reg_13_ } \
    { cell r1_reg[14] r1_reg_14_ } \
    { cell r15_reg[14] r15_reg_14_ } \
    { cell r14_reg[14] r14_reg_14_ } \
    { cell r13_reg[14] r13_reg_14_ } \
    { cell r12_reg[14] r12_reg_14_ } \
    { cell r11_reg[14] r11_reg_14_ } \
    { cell r10_reg[14] r10_reg_14_ } \
    { cell r9_reg[14] r9_reg_14_ } \
    { cell r8_reg[14] r8_reg_14_ } \
    { cell r7_reg[14] r7_reg_14_ } \
    { cell r6_reg[14] r6_reg_14_ } \
    { cell r5_reg[14] r5_reg_14_ } \
    { cell r4_reg[14] r4_reg_14_ } \
    { cell r2_reg[2] r2_reg_2_ } \
    { cell r3_reg[15] r3_reg_15_ } \
    { cell r2_reg[1] r2_reg_1_ } \
    { cell r1_reg[15] r1_reg_15_ } \
    { cell r15_reg[15] r15_reg_15_ } \
    { cell r14_reg[15] r14_reg_15_ } \
    { cell r13_reg[15] r13_reg_15_ } \
    { cell r12_reg[15] r12_reg_15_ } \
    { cell r11_reg[15] r11_reg_15_ } \
    { cell r10_reg[15] r10_reg_15_ } \
    { cell r9_reg[15] r9_reg_15_ } \
    { cell r8_reg[15] r8_reg_15_ } \
    { cell r7_reg[15] r7_reg_15_ } \
    { cell r6_reg[15] r6_reg_15_ } \
    { cell r5_reg[15] r5_reg_15_ } \
    { cell r4_reg[15] r4_reg_15_ } \
    { cell r2_reg[8] r2_reg_8_ } \
    { cell r2_reg[0] r2_reg_0_ } \
    { net r2[9] r2_9_ } \
    { net r15[15] test_so } \
    { net r15[14] r15_14_ } \
    { net r15[13] r15_13_ } \
    { net r15[12] r15_12_ } \
    { net r15[11] r15_11_ } \
    { net r15[10] r15_10_ } \
    { net r15[9] r15_9_ } \
    { net r15[8] r15_8_ } \
    { net r15[7] r15_7_ } \
    { net r15[6] r15_6_ } \
    { net r15[5] r15_5_ } \
    { net r15[4] r15_4_ } \
    { net r15[3] r15_3_ } \
    { net r15[2] r15_2_ } \
    { net r15[1] r15_1_ } \
    { net r15[0] r15_0_ } } 

guide_change_names \
  -design { omsp_alu } \
  { { net inst_so_7 inst_so[7] } \
    { net inst_so_3 inst_so[3] } \
    { net DP_OP_68J4_125_7159/n44 DP_OP_68J4_125_7159_n44 } \
    { net DP_OP_68J4_125_7159/n43 DP_OP_68J4_125_7159_n43 } \
    { net DP_OP_68J4_125_7159/n42 DP_OP_68J4_125_7159_n42 } \
    { net DP_OP_68J4_125_7159/n41 DP_OP_68J4_125_7159_n41 } \
    { net DP_OP_68J4_125_7159/n34 DP_OP_68J4_125_7159_n34 } \
    { net DP_OP_68J4_125_7159/n33 DP_OP_68J4_125_7159_n33 } \
    { net DP_OP_68J4_125_7159/n32 DP_OP_68J4_125_7159_n32 } \
    { net DP_OP_68J4_125_7159/n3 DP_OP_68J4_125_7159_n3 } \
    { net DP_OP_68J4_125_7159/n2 DP_OP_68J4_125_7159_n2 } \
    { net intadd_5/A[14] intadd_5_A_14_ } \
    { net intadd_5/A[13] intadd_5_A_13_ } \
    { net intadd_5/A[12] intadd_5_A_12_ } \
    { net intadd_5/A[10] intadd_5_A_10_ } \
    { net intadd_5/A[9] intadd_5_A_9_ } \
    { net intadd_5/A[8] intadd_5_A_8_ } \
    { net intadd_5/A[7] intadd_5_A_7_ } \
    { net intadd_5/B[14] intadd_5_B_14_ } \
    { net intadd_5/B[13] intadd_5_B_13_ } \
    { net intadd_5/B[12] intadd_5_B_12_ } \
    { net intadd_5/B[11] intadd_5_B_11_ } \
    { net intadd_5/B[10] intadd_5_B_10_ } \
    { net intadd_5/B[9] intadd_5_B_9_ } \
    { net intadd_5/B[8] intadd_5_B_8_ } \
    { net intadd_5/B[7] intadd_5_B_7_ } \
    { net intadd_5/B[6] intadd_5_B_6_ } \
    { net intadd_5/B[4] intadd_5_B_4_ } \
    { net intadd_5/B[3] intadd_5_B_3_ } \
    { net intadd_5/B[2] intadd_5_B_2_ } \
    { net intadd_5/B[1] intadd_5_B_1_ } \
    { net intadd_5/n15 intadd_5_n15 } \
    { net intadd_5/n14 intadd_5_n14 } \
    { net intadd_5/n13 intadd_5_n13 } \
    { net intadd_5/n12 intadd_5_n12 } \
    { net intadd_5/n11 intadd_5_n11 } \
    { net intadd_5/n10 intadd_5_n10 } \
    { net intadd_5/n9 intadd_5_n9 } \
    { net intadd_5/n8 intadd_5_n8 } \
    { net intadd_5/n7 intadd_5_n7 } \
    { net intadd_5/n6 intadd_5_n6 } \
    { net intadd_5/n5 intadd_5_n5 } \
    { net intadd_5/n4 intadd_5_n4 } \
    { net intadd_5/n3 intadd_5_n3 } \
    { net intadd_5/n2 intadd_5_n2 } \
    { net intadd_5/n1 intadd_5_n1 } } 

guide_change_names \
  -design { omsp_wakeup_cell_0 } \
  { { net *Logic1* n_Logic1_ } } 

guide_change_names \
  -design { omsp_sync_cell_5 } \
  { { cell data_sync_reg[0] data_sync_reg_0_ } \
    { cell data_sync_reg[1] data_sync_reg_1_ } } 

guide_change_names \
  -design { omsp_clock_mux_1 } \
  { { net in1_select_ss test_so4 } \
    { net in0_select_s test_so1 } \
    { net in0_select_ss test_so3 } \
    { net in1_select_s test_so2 } } 

guide_change_names \
  -design { omsp_sync_reset_1 } \
  { { cell data_sync_reg[0] data_sync_reg_0_ } \
    { cell data_sync_reg[1] data_sync_reg_1_ } \
    { net *Logic0* n_Logic0_ } \
    { net data_sync[0] data_sync_0_ } } 

guide_change_names \
  -design { omsp_sync_cell_4 } \
  { { cell data_sync_reg[0] data_sync_reg_0_ } \
    { cell data_sync_reg[1] data_sync_reg_1_ } } 

guide_change_names \
  -design { omsp_sync_cell_3 } \
  { { cell data_sync_reg[0] data_sync_reg_0_ } \
    { cell data_sync_reg[1] data_sync_reg_1_ } } 

guide_change_names \
  -design { omsp_sync_cell_2 } \
  { { cell data_sync_reg[0] data_sync_reg_0_ } \
    { cell data_sync_reg[1] data_sync_reg_1_ } } 

guide_change_names \
  -design { omsp_wakeup_cell_1 } \
  { { net *Logic1* n_Logic1_ } } 

guide_change_names \
  -design { omsp_dbg_uart } \
  { { cell xfer_buf_reg[18] xfer_buf_reg_18_ } \
    { cell uart_state_reg[0] uart_state_reg_0_ } \
    { cell xfer_bit_reg[0] xfer_bit_reg_0_ } \
    { cell xfer_bit_reg[3] xfer_bit_reg_3_ } \
    { cell xfer_buf_reg[19] xfer_buf_reg_19_ } \
    { cell xfer_bit_reg[2] xfer_bit_reg_2_ } \
    { cell xfer_bit_reg[1] xfer_bit_reg_1_ } \
    { cell uart_state_reg[2] uart_state_reg_2_ } \
    { cell uart_state_reg[1] uart_state_reg_1_ } \
    { cell sync_cnt_reg[17] sync_cnt_reg_17_ } \
    { cell sync_cnt_reg[16] sync_cnt_reg_16_ } \
    { cell sync_cnt_reg[15] sync_cnt_reg_15_ } \
    { cell sync_cnt_reg[14] sync_cnt_reg_14_ } \
    { cell sync_cnt_reg[13] sync_cnt_reg_13_ } \
    { cell sync_cnt_reg[12] sync_cnt_reg_12_ } \
    { cell sync_cnt_reg[11] sync_cnt_reg_11_ } \
    { cell sync_cnt_reg[10] sync_cnt_reg_10_ } \
    { cell sync_cnt_reg[9] sync_cnt_reg_9_ } \
    { cell sync_cnt_reg[8] sync_cnt_reg_8_ } \
    { cell sync_cnt_reg[7] sync_cnt_reg_7_ } \
    { cell sync_cnt_reg[6] sync_cnt_reg_6_ } \
    { cell sync_cnt_reg[5] sync_cnt_reg_5_ } \
    { cell sync_cnt_reg[4] sync_cnt_reg_4_ } \
    { cell sync_cnt_reg[3] sync_cnt_reg_3_ } \
    { cell sync_cnt_reg[2] sync_cnt_reg_2_ } \
    { cell sync_cnt_reg[1] sync_cnt_reg_1_ } \
    { cell sync_cnt_reg[0] sync_cnt_reg_0_ } \
    { cell sync_cnt_reg[18] sync_cnt_reg_18_ } \
    { cell xfer_cnt_reg[0] xfer_cnt_reg_0_ } \
    { cell xfer_cnt_reg[15] xfer_cnt_reg_15_ } \
    { cell xfer_cnt_reg[14] xfer_cnt_reg_14_ } \
    { cell xfer_cnt_reg[13] xfer_cnt_reg_13_ } \
    { cell xfer_cnt_reg[12] xfer_cnt_reg_12_ } \
    { cell xfer_cnt_reg[11] xfer_cnt_reg_11_ } \
    { cell xfer_cnt_reg[10] xfer_cnt_reg_10_ } \
    { cell xfer_cnt_reg[9] xfer_cnt_reg_9_ } \
    { cell xfer_cnt_reg[8] xfer_cnt_reg_8_ } \
    { cell xfer_cnt_reg[7] xfer_cnt_reg_7_ } \
    { cell xfer_cnt_reg[6] xfer_cnt_reg_6_ } \
    { cell xfer_cnt_reg[5] xfer_cnt_reg_5_ } \
    { cell xfer_cnt_reg[4] xfer_cnt_reg_4_ } \
    { cell xfer_cnt_reg[3] xfer_cnt_reg_3_ } \
    { cell xfer_cnt_reg[2] xfer_cnt_reg_2_ } \
    { cell xfer_cnt_reg[1] xfer_cnt_reg_1_ } \
    { cell xfer_buf_reg[17] xfer_buf_reg_17_ } \
    { cell xfer_buf_reg[9] xfer_buf_reg_9_ } \
    { cell xfer_buf_reg[4] xfer_buf_reg_4_ } \
    { cell xfer_buf_reg[3] xfer_buf_reg_3_ } \
    { cell dbg_addr_reg[5] dbg_addr_reg_5_ } \
    { cell dbg_addr_reg[4] dbg_addr_reg_4_ } \
    { cell dbg_addr_reg[3] dbg_addr_reg_3_ } \
    { cell dbg_addr_reg[2] dbg_addr_reg_2_ } \
    { cell dbg_addr_reg[1] dbg_addr_reg_1_ } \
    { cell dbg_addr_reg[0] dbg_addr_reg_0_ } \
    { cell xfer_buf_reg[16] xfer_buf_reg_16_ } \
    { cell xfer_buf_reg[15] xfer_buf_reg_15_ } \
    { cell xfer_buf_reg[14] xfer_buf_reg_14_ } \
    { cell xfer_buf_reg[12] xfer_buf_reg_12_ } \
    { cell xfer_buf_reg[2] xfer_buf_reg_2_ } \
    { cell xfer_buf_reg[1] xfer_buf_reg_1_ } \
    { cell xfer_buf_reg[0] xfer_buf_reg_0_ } \
    { cell xfer_buf_reg[10] xfer_buf_reg_10_ } \
    { cell xfer_buf_reg[8] xfer_buf_reg_8_ } \
    { cell xfer_buf_reg[7] xfer_buf_reg_7_ } \
    { cell xfer_buf_reg[6] xfer_buf_reg_6_ } \
    { cell xfer_buf_reg[5] xfer_buf_reg_5_ } \
    { cell rxd_buf_reg[0] rxd_buf_reg_0_ } \
    { cell rxd_buf_reg[1] rxd_buf_reg_1_ } \
    { cell xfer_buf_reg[13] xfer_buf_reg_13_ } \
    { cell xfer_buf_reg[11] xfer_buf_reg_11_ } \
    { net rxd_buf[1] test_so1 } \
    { net rxd_buf[0] rxd_buf_0_ } \
    { net xfer_cnt[15] test_so2 } \
    { net xfer_cnt[14] xfer_cnt_14_ } \
    { net xfer_cnt[13] xfer_cnt_13_ } \
    { net xfer_cnt[12] xfer_cnt_12_ } \
    { net xfer_cnt[11] xfer_cnt_11_ } \
    { net xfer_cnt[10] xfer_cnt_10_ } \
    { net xfer_cnt[9] xfer_cnt_9_ } \
    { net xfer_cnt[8] xfer_cnt_8_ } \
    { net xfer_cnt[7] xfer_cnt_7_ } \
    { net xfer_cnt[6] xfer_cnt_6_ } \
    { net xfer_cnt[5] xfer_cnt_5_ } \
    { net xfer_cnt[4] xfer_cnt_4_ } \
    { net xfer_cnt[3] xfer_cnt_3_ } \
    { net xfer_cnt[2] xfer_cnt_2_ } \
    { net xfer_cnt[1] xfer_cnt_1_ } \
    { net xfer_cnt[0] xfer_cnt_0_ } \
    { net xfer_buf[0] xfer_buf_0_ } } 

guide_change_names \
  -design { omsp_sync_cell_1 } \
  { { cell data_sync_reg[0] data_sync_reg_0_ } \
    { cell data_sync_reg[1] data_sync_reg_1_ } } 

guide_environment \
  { { write_file { -format verilog -hierarchy -output ./results/openMSP430.gate.v } } \
    { write_file { -format verilog -hierarchy -output ./netlist/openMSP430_blah.v } } \
    { write_file { -format ddc -hierarchy -output ./results/openMSP430.ddc } } \
    { current_design openMSP430 } } 

guide_environment \
  { { current_design openMSP430 } } 

#---- Recording stopped at Sat Apr 28 22:06:01 2012

setup
